[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/ptl: Enable FSP debug log level control using CBFS

[Subrata Banik (Code Review)]

Attention is currently required from: Intel coreboot Reviewers, Kapil Porwal, Pranava Y N.

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86002?usp=email )

Change subject: soc/intel/ptl: Enable FSP debug log level control using CBFS
......................................................................

soc/intel/ptl: Enable FSP debug log level control using CBFS

This commit enables the FSP_DEBUG_LOG_LEVEL_USING_CBFS Kconfig option
for Panther Lake ChromeOS devices.

This allows controlling the FSP debug log level using CBFS RAW binary
files, providing more flexibility in debugging silicon firmware issues
with a debug AP FW binary.

The following CBFS files are used to determine the log levels:

- fsp_pcd_debug_level: For the overall FSP debug log level.
- fsp_mrc_debug_level: For the MRC (Memory Reference Code) debug log
  level.

Refer to the Kconfig help text for FSP_DEBUG_LOG_LEVEL_USING_CBFS for
details on the valid log level values and how to set them using
cbfstool.

This capability is particularly useful when debugging issues that require
examining both silicon and MRC logs simultaneously.

BUG=b:227151510
TEST=Able to control the FSP debug log based on CBFS options

To inject the fsp_pcd_debug_level and fsp_mrc_debug_level CBFS files
with the desired log level, run:

```
cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_pcd_debug_level

cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_mrc_debug_level
```

Change-Id: Ia2fc07188afde34d61ce8d50d3d722de48228e37
Signed-off-by: Subrata Banik 
---
M src/soc/intel/pantherlake/Kconfig
M src/soc/intel/pantherlake/fsp_params.c
M src/soc/intel/pantherlake/romstage/fsp_params.c
3 files changed, 12 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/86002/1

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 4f6f658..311520c 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -16,6 +16,7 @@
    select DRIVERS_USB_ACPI
    select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
    select FSP_COMPRESS_FSP_S_LZ4
+	select FSP_DEBUG_LOG_LEVEL_USING_CBFS if MAINBOARD_HAS_CHROMEOS
    select FSP_M_XIP
    select FSP_UGOP_EARLY_SIGN_OF_LIFE
    select FSP_USES_CB_DEBUG_EVENT_HANDLER
diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c
index dfc47c6..8a5754e 100644
--- a/src/soc/intel/pantherlake/fsp_params.c
+++ b/src/soc/intel/pantherlake/fsp_params.c
@@ -3,6 +3,7 @@
 #include <bootmode.h>
 #include <cpu/intel/microcode.h>
 #include <fsp/api.h>
+#include <fsp/debug.h>
 #include <fsp/fsp_debug_event.h>
 #include <fsp/fsp_gop_blt.h>
 #include <fsp/ppi/mp_service_ppi.h>
@@ -685,7 +686,7 @@
    /* Assign FspEventHandler arch Upd to use coreboot debug event handler */
    if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)
        && CONFIG(CONSOLE_SERIAL)
-	    && CONFIG(FSP_ENABLE_SERIAL_DEBUG))
+	    && CONFIG(FSP_ENABLE_SERIAL_DEBUG) && get_fsp_pcd_debug_log_level())
    	s_arch_cfg->FspEventHandler = (uintptr_t)((FSP_EVENT_HANDLER *)
    						  fsp_debug_event_handler);

diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index 033c4ea..464d925 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -2,6 +2,7 @@

#include <cpu/intel/common/common.h>
 #include <cpu/x86/msr.h>
+#include <fsp/debug.h>
 #include <fsp/fsp_debug_event.h>
 #include <fsp/util.h>
 #include <intelblocks/cpulib.h>
@@ -310,9 +311,14 @@
    FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
    FSPM_ARCHx_UPD *arch_upd = &mupd->FspmArchUpd;

-	enum fsp_log_level log_level = is_enabled ? fsp_map_console_log_level() :
-		 FSP_LOG_LEVEL_DISABLE;
-	fsp_set_debug_level(m_cfg, log_level, log_level);
+	if (CONFIG(FSP_DEBUG_LOG_LEVEL_USING_CBFS) && is_enabled) {
+		fsp_set_debug_level(m_cfg, get_fsp_pcd_debug_log_level(),
+			 get_fsp_mrc_debug_log_level());
+	} else {
+		enum fsp_log_level log_level = is_enabled ? fsp_map_console_log_level() :
+			 FSP_LOG_LEVEL_DISABLE;
+		fsp_set_debug_level(m_cfg, log_level, log_level);
+	}

if ((m_cfg->PcdSerialDebugLevel > FSP_LOG_LEVEL_VERBOSE) ||
        (m_cfg->SerialDebugMrcLevel > FSP_LOG_LEVEL_VERBOSE)) {