[coreboot-gerrit] Change in coreboot[master]: soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI reads

[Raul Rangel (Code Review)]

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55987 )

Change subject: soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI reads
......................................................................

soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI reads

We are currently reading the uCode for each CPU. This is unnecessary
since the uCode never changes.

BUG=b:177909625
TEST=Boot guybrush and see "microcode: being updated to patch id" for
each CPU. I no longer see CBFS access for each CPU. This drops device
initialization time by 32 ms.

Signed-off-by: Raul E Rangel 
Change-Id: I98b9d4ce8290a1f08063176809e903e671663208
---
M src/soc/amd/common/block/cpu/update_microcode.c
1 file changed, 20 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/55987/1

diff --git a/src/soc/amd/common/block/cpu/update_microcode.c b/src/soc/amd/common/block/cpu/update_microcode.c
index 2ba1802..4968fa3 100644
--- a/src/soc/amd/common/block/cpu/update_microcode.c
+++ b/src/soc/amd/common/block/cpu/update_microcode.c
@@ -14,6 +14,9 @@
 #define MPB_MAX_SIZE CONFIG_SOC_AMD_COMMON_BLOCK_UCODE_SIZE
 #define MPB_DATA_OFFSET 32

+bool buffer_valid;
+uint8_t buffer[CONFIG_SOC_AMD_COMMON_BLOCK_UCODE_SIZE];
+
 struct microcode {
    uint32_t date_code;
    uint32_t patch_id;
@@ -83,11 +86,23 @@
    size_t ucode_len;
    uint16_t equivalent_processor_rev_id = get_equivalent_processor_rev_id();

-	ucode = cbfs_map("cpu_microcode_blob.bin", &ucode_len);
-	if (!ucode) {
-		printk(BIOS_WARNING, "cpu_microcode_blob.bin not found. Skipping updates.\n");
-		return;
+	/* Cache the buffer so each CPU doesn't need to read the uCode from flash */
+	if (!buffer_valid) {
+		ucode = cbfs_map("cpu_microcode_blob.bin", &ucode_len);
+		if (!ucode) {
+			printk(BIOS_WARNING, "cpu_microcode_blob.bin not found. Skipping updates.\n");
+			return;
+		}
+
+		if (ucode_len != CONFIG_SOC_AMD_COMMON_BLOCK_UCODE_SIZE) {
+			printk(BIOS_WARNING,
+			       "cpu_microcode_blob.bin has unexpected size %zu.\n", ucode_len);
+			return;
+		}
+		memcpy(buffer, ucode, ucode_len);
+
+		buffer_valid = true;
    }

-	amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id);
+	amd_update_microcode(buffer, sizeof(buffer), equivalent_processor_rev_id);
 }