16 Nov
2020
16 Nov
'20
8:42 p.m.
Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47644 )
Change subject: soc/intel/alderlake: Fix overlapping memory address used for early GSPI2 and UART bars ......................................................................
Patch Set 1:
Aamir, I don't have alderlake platform to check, can you please help check?
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3249a91df8a2e319aff6303ef9400e74163afe93
Gerrit-Change-Number: 47644
Gerrit-PatchSet: 1
Gerrit-Owner: Bora Guvendik bora.guvendik@intel.com
Gerrit-Reviewer: Aamir Bohra aamir.bohra@intel.com
Gerrit-Reviewer: Furquan Shaikh furquan@google.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: Selma Bensaid selma.bensaid@intel.com
Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com
Gerrit-Comment-Date: Mon, 16 Nov 2020 19:42:25 +0000
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