[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Fix PCI interrupts for D31

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39445 )

Change subject: soc/intel/tigerlake: Fix PCI interrupts for D31
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Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39445/2/src/soc/intel/tigerlake/acp... 
File src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl:

https://review.coreboot.org/c/coreboot/+/39445/2/src/soc/intel/tigerlake/acp... 
PS2, Line 21: Package(){0x001FFFFF, 0, 0, eSPI_IRQ },
            : 	Package(){0x001FFFFF, 1, 0, P2SB_IRQ },
            : 	Package(){0x001FFFFF, 2, 0, PMC_IRQ },
> So, which setting is taking effect? Can you please point me to the right code?

It's not part of FSP code but FSP wrapper code.  I'll create partner bug to share part of code.