Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39135 )
Change subject: src/soc/tigerlake: Add memory configuration support for Jasper Lake ......................................................................
Patch Set 14:
(4 comments)
https://review.coreboot.org/c/coreboot/+/39135/7/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/jsl_memcfg_init.h:
https://review.coreboot.org/c/coreboot/+/39135/7/src/soc/intel/tigerlake/inc... PS7, Line 103: uint16_t rcomp_resistor[3];
In JSL, we can't auto configure it as the board values deviates and need to be passed in mainboard.
https://review.coreboot.org/c/coreboot/+/39135/7/src/soc/intel/tigerlake/inc... PS7, Line 116: dq_pins_interleaved
Does JSL with LPDDR4 allow interleaved memory configuration? I know with TGL this was not a possibil […]
Furquan, i understand your concern that interleaved might not required here as FSP default and coreboot UPD over ride both sets to 0 hence we can avoid the same, but be in safer side, i might need to get this confirmation from HW team. Can we do additional clean up if required to remove interleaved later?
https://review.coreboot.org/c/coreboot/+/39135/2/src/soc/intel/tigerlake/jsl... File src/soc/intel/tigerlake/jsl_memcfg_init.c:
https://review.coreboot.org/c/coreboot/+/39135/2/src/soc/intel/tigerlake/jsl... PS2, Line 139: NOT_EXISTING:
Ok, I believe that means we don't need to pass the strap information regarding only half the memory […]
Yes, This is not applicable to JSL. Hence we would not be using the half populated memory modules type of configuration.
https://review.coreboot.org/c/coreboot/+/39135/7/src/soc/intel/tigerlake/jsl... File src/soc/intel/tigerlake/jsl_memcfg_init.c:
https://review.coreboot.org/c/coreboot/+/39135/7/src/soc/intel/tigerlake/jsl... PS7, Line 136: for (int i = 0; i < NUM_DIMM_SLOT; i++) {
I think some of these can be simplified based on what the memory controller really supports. […]
Done