Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29394
Change subject: src/soc/intel/braswell/hda.c: Codecs connected to HDA are configured ......................................................................
src/soc/intel/braswell/hda.c: Codecs connected to HDA are configured
The support of the HDA did not configure the codecs. Add hda_init() and hda_enable() to configure the codecs.
BUG=N/A TEST=Intel CherryHill CRB
Change-Id: I5c23ec311e5b5a6dfd6f031aa19617407fe8ed63 Signed-off-by: Frans Hendriks fhendriks@eltan.com --- M src/soc/intel/braswell/hda.c M src/soc/intel/braswell/include/soc/ramstage.h M src/soc/intel/braswell/southcluster.c 3 files changed, 71 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/29394/1
diff --git a/src/soc/intel/braswell/hda.c b/src/soc/intel/braswell/hda.c index a92d7a9..310de28 100644 --- a/src/soc/intel/braswell/hda.c +++ b/src/soc/intel/braswell/hda.c @@ -3,6 +3,7 @@ * * Copyright (C) 2014 Google Inc. * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,27 +14,82 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include <arch/io.h> #include <console/console.h> #include <device/device.h> +#include <device/azalia_device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ids.h> -#include <reg_script.h> - -#include <soc/hda.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> +#include <device/pci_ops.h> +#include <arch/io.h> +#include <delay.h> +#include <soc/intel/common/hda_verb.h> #include <soc/ramstage.h>
+static void codecs_init(u8 *base, u32 codec_mask) +{ + int i; + + /* Can support up to 4 codecs */ + for (i = 3; i >= 0; i--) { + if (codec_mask & (1 << i)) + hda_codec_init(base, i, + cim_verb_data_size, + cim_verb_data); + } + + if (pc_beep_verbs_size) + hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs); +} + +static void hda_init(struct device *dev) +{ + u8 *base; + struct resource *res; + u32 codec_mask; + u32 reg32; + + /* Find base address */ + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (!res) + return; + + base = res2mmio(res, 0, 0); + printk(BIOS_DEBUG, "HDA: base = %p\n", base); + + /* Set Bus Master */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); + + codec_mask = hda_codec_detect(base); + + if (codec_mask) { + printk(BIOS_DEBUG, "HDA: codec_mask = %02x\n", codec_mask); + codecs_init(base, codec_mask); + } +} +static void hda_enable(struct device *dev) +{ + u32 reg32; + + if (!dev->enabled) { + /* Ensure memory, io, and bus master are all disabled */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~(PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Disable this device */ + sc_disable_devfn(dev); + } +} static const struct device_operations device_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = NULL, - .enable = NULL, - .scan_bus = NULL, - .ops_pci = &soc_pci_ops, + .init = hda_init, + .enable = hda_enable, + .scan_bus = NULL, + .ops_pci = &soc_pci_ops, };
static const struct pci_driver southcluster __pci_driver = { diff --git a/src/soc/intel/braswell/include/soc/ramstage.h b/src/soc/intel/braswell/include/soc/ramstage.h index d735de5..696e9d1 100644 --- a/src/soc/intel/braswell/include/soc/ramstage.h +++ b/src/soc/intel/braswell/include/soc/ramstage.h @@ -3,6 +3,7 @@ * * Copyright (C) 2013 Google Inc. * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -99,6 +100,7 @@ void soc_init_cpus(struct device *dev); void set_max_freq(void); void southcluster_enable_dev(struct device *dev); +void sc_disable_devfn(struct device *dev); void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index); int SocStepping(void); void board_silicon_USB2_override(SILICON_INIT_UPD *params); diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index ca87d63..2349501 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -198,8 +198,8 @@ * Common code for the south cluster devices. */
-/* Set bit in function disble register to hide this device. */ -static void sc_disable_devfn(struct device *dev) +/* Set bit in function disable register to hide this device. */ +void sc_disable_devfn(struct device *dev) { void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS); void *func_dis2 = (void *)(PMC_BASE_ADDRESS + FUNC_DIS2);