[coreboot-gerrit] [XS] Change in coreboot[main]: soc/mediatek/mt8196: Delay 0.5ms after enabling PMIF SPMI SW interface

[Yidi Lin (Code Review)]

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85799?usp=email )

Change subject: soc/mediatek/mt8196: Delay 0.5ms after enabling PMIF SPMI SW interface
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soc/mediatek/mt8196: Delay 0.5ms after enabling PMIF SPMI SW interface

The initialization process of SPMI requires a certain amount of time
(0.5ms) to ensure all components are correctly configured and
synchronized. Otherwise, if the SPMI calibration fails, it will result
in the non-serial firmware failing to boot.

TEST=Build pass, non-serial firmware boot ok.
BUG=b:341054056

Change-Id: I63df384061e4ed2629238f1843decd18d1ad1ac4
Signed-off-by: Hope Wang 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85799
Tested-by: build bot (Jenkins) 
Reviewed-by: Yu-Ping Wu 
Reviewed-by: Yidi Lin 
---
M src/soc/mediatek/mt8196/pmif_spmi.c
1 file changed, 2 insertions(+), 0 deletions(-)

Approvals:
  Yu-Ping Wu: Looks good to me, approved
  Yidi Lin: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/soc/mediatek/mt8196/pmif_spmi.c b/src/soc/mediatek/mt8196/pmif_spmi.c
index d00afe1..e646816 100644
--- a/src/soc/mediatek/mt8196/pmif_spmi.c
+++ b/src/soc/mediatek/mt8196/pmif_spmi.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */

#include <console/console.h>
+#include <delay.h>
 #include <device/mmio.h>
 #include <gpio.h>
 #include <soc/addressmap.h>
@@ -285,6 +286,7 @@
 {
    write32(&arb->mtk_pmif->inf_en, PMIF_SPMI_SW_CHAN);
    write32(&arb->mtk_pmif->arb_en, PMIF_SPMI_SW_CHAN);
+	udelay(500);
    printk(BIOS_INFO, "%s done\n", __func__);
 }