Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40817 )
Change subject: mb/google/kahlee: Start PCIe reset sooner on careena devices ......................................................................
mb/google/kahlee: Start PCIe reset sooner on careena devices
The realtek RTL8822CE wifi module needs a PCIe reset of at least 6ms instead of the ~200us reset that is typically done by AGESA. By starting the reset earlier, we get a longer reset without making the boot time any longer.
BUG=b:154357210 BRANCH=firmware-grunt-11031.B TEST=Check reset on a scope. This change results in an 18ms delay roughly 425ms after power on. RTL8822CE module works.
Signed-off-by: Martin Roth martinroth@chromium.org Change-Id: If2d2c72445daeea8567b8ee989533785c35667e8 --- M src/mainboard/google/kahlee/variants/careena/Makefile.inc M src/mainboard/google/kahlee/variants/careena/variant.c M src/soc/amd/stoneyridge/include/soc/southbridge.h 3 files changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/40817/1
diff --git a/src/mainboard/google/kahlee/variants/careena/Makefile.inc b/src/mainboard/google/kahlee/variants/careena/Makefile.inc index d24c19b..dd9ff4e 100644 --- a/src/mainboard/google/kahlee/variants/careena/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/careena/Makefile.inc @@ -14,6 +14,6 @@
subdirs-y += ./spd
-+romstage-y += variant.c +romstage-y += variant.c
ramstage-y += ../baseboard/mainboard.c diff --git a/src/mainboard/google/kahlee/variants/careena/variant.c b/src/mainboard/google/kahlee/variants/careena/variant.c index d35ec48..5517eb1 100644 --- a/src/mainboard/google/kahlee/variants/careena/variant.c +++ b/src/mainboard/google/kahlee/variants/careena/variant.c @@ -15,6 +15,7 @@
#include <ec/google/chromeec/ec.h> #include <baseboard/variants.h> +#include <soc/southbridge.h> #include <variant/sku.h>
void variant_romstage_entry(int s3_resume) @@ -34,5 +35,6 @@ google_chromeec_kbbacklight(10); break; } + pm_write8(PM_RST_CMD, pm_read8(PM_RST_CMD) | PM_RESET_PCIE); } } diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 69210b7..10ed3ff 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -81,6 +81,8 @@ #define PM_RST_CTRL1 0xbe #define SLPTYPE_CONTROL_EN BIT(5) #define PM_RST_STATUS 0xc0 +#define PM_RST_CMD 0xc4 +#define PM_RESET_PCIE BIT(4) #define PM_PCIB_CFG 0xea #define PM_GENINT_DISABLE BIT(0) #define PM_LPC_GATING 0xec