Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46411 )
Change subject: soc/mediatek/mt8192: Add function to raise the CCI frequency ......................................................................
soc/mediatek/mt8192: Add function to raise the CCI frequency
Implement mt_pll_raise_cci_freq() in MT8192 to raise the CCI frequency. Usage: mt_pll_raise_cci_freq(1400UL * MHz);
Signed-off-by: Weiyi Lu weiyi.lu@mediatek.com Change-Id: I084cd7888b1dcfdeaef308b8bb3677d034497a30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46411 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Yu-Ping Wu yupingso@google.com --- M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/mt8192/pll.c 2 files changed, 26 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved
diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h index ae6ad64..cb22796 100644 --- a/src/soc/mediatek/common/include/soc/pll_common.h +++ b/src/soc/mediatek/common/include/soc/pll_common.h @@ -69,6 +69,7 @@ int pll_set_rate(const struct pll *pll, u32 rate); void mt_pll_init(void); void mt_pll_raise_little_cpu_freq(u32 freq); +void mt_pll_raise_cci_freq(u32 freq);
enum fmeter_type { FMETER_ABIST = 0, diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index 6d61fb4..f0a9509 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -559,3 +559,28 @@
return 0; } + +void mt_pll_raise_cci_freq(u32 freq) +{ + /* enable [4] intermediate clock armpll_divider_pll1_ck */ + setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); + + /* switch cci clock source to intermediate clock */ + clrsetbits32(&mt8192_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_DIV_PLL1); + + /* disable ccipll frequency output */ + clrbits32(plls[APMIXED_CCIPLL].reg, PLL_EN); + + /* raise ccipll frequency */ + pll_set_rate(&plls[APMIXED_CCIPLL], freq); + + /* enable ccipll frequency output */ + setbits32(plls[APMIXED_CCIPLL].reg, PLL_EN); + udelay(PLL_EN_DELAY); + + /* switch cci clock source back to ccipll */ + clrsetbits32(&mt8192_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + + /* disable [4] intermediate clock armpll_divider_pll1_ck */ + clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); +}