Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34995 )
Change subject: arch/x86: Cache the TSEG region at the top of ram ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34995/3/src/arch/x86/postcar_loader... File src/arch/x86/postcar_loader.c:
https://review.coreboot.org/c/coreboot/+/34995/3/src/arch/x86/postcar_loader... PS3, Line 153: MTRR_TYPE_WRBACK);
Remember what I wrote earlier about postcar_frame_setup_top_of_dram_usage() setting new requirements for the alignments, should you call set_var_mtrr() from inside of it? That's why it is currently being rejected.
set_var_mtrr() been used here to enable immediate caching of give range. if we had to relying on "postcar_frame_add_mtrr()", it would be taken care during next stage entry point only while setting up new MTRR range.
Also just to note: i'm not calling "set_var_mtrr()" function here atleast in this CL. isn't it ?