[coreboot-gerrit] Change in coreboot[master]: mb/intel/adlrvp: Disable dq_pins_interleaved for DDR4/5 RVP

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48078 )

Change subject: mb/intel/adlrvp: Disable dq_pins_interleaved for DDR4/5 RVP
......................................................................

mb/intel/adlrvp: Disable dq_pins_interleaved for DDR4/5 RVP

TEST=Able to pass MRC training on DDR4/5 SKUs

Change-Id: I38fcb17a1be5a8544a17cef8255631b6abef0741
Signed-off-by: Subrata Banik 
---
M src/mainboard/intel/adlrvp/memory.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/48078/1

diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c
index c25b245..66ae55e 100644
--- a/src/mainboard/intel/adlrvp/memory.c
+++ b/src/mainboard/intel/adlrvp/memory.c
@@ -12,7 +12,7 @@
    /* Baseboard Rcomp target values */
    .rcomp_targets = {40, 30, 33, 33, 30},

-	.dq_pins_interleaved = true,
+	.dq_pins_interleaved = false,

.ect = true, /* Early Command Training */

@@ -51,7 +51,7 @@
    /* Baseboard Rcomp target values */
    .rcomp_targets = {50, 30, 30, 30, 27},

-	.dq_pins_interleaved = true,
+	.dq_pins_interleaved = false,

.ect = true, /* Early Command Training */