Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58538 )
Change subject: mainboard/starlabs: Add LabTop Mk III ......................................................................
mainboard/starlabs: Add LabTop Mk III
Tested using MrChromeBox's `uefipayload_202107` branch: * Windows 10 * Ubuntu 20.04 * MX Linux 19.4 * Manjaro 21
Everything works correctly.
https://starlabs.systems/pages/labtop-mk-iii-specification
Signed-off-by: Sean Rhodes sean@starlabs.systems Change-Id: Ia52566e06f50c0abcfb657044538db8e92564c36 --- M Documentation/mainboard/index.md A Documentation/mainboard/starlabs/labtop_kbl.md M src/mainboard/starlabs/labtop/Kconfig M src/mainboard/starlabs/labtop/Kconfig.name A src/mainboard/starlabs/labtop/acpi/ec.asl A src/mainboard/starlabs/labtop/acpi/superio.asl M src/mainboard/starlabs/labtop/dsdt.asl M src/mainboard/starlabs/labtop/mainboard.c A src/mainboard/starlabs/labtop/spd/spd.h A src/mainboard/starlabs/labtop/spd/spd_util.c M src/mainboard/starlabs/labtop/variants/cml/devicetree.cb A src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc A src/mainboard/starlabs/labtop/variants/kbl/board.fmd A src/mainboard/starlabs/labtop/variants/kbl/data.vbt A src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb A src/mainboard/starlabs/labtop/variants/kbl/devtree.c A src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads A src/mainboard/starlabs/labtop/variants/kbl/gpio.c A src/mainboard/starlabs/labtop/variants/kbl/hda_verb.c A src/mainboard/starlabs/labtop/variants/kbl/romstage.c 20 files changed, 900 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/58538/1
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 65ce133..7d701ee 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -174,6 +174,7 @@
## Star Labs Systems
+- [LabTop Mk III](starlabs/labtop_kbl.md) - [LabTop Mk IV](starlabs/labtop_cml.md) - [StarBook Mk V](starlabs/starbook_tgl.md)
diff --git a/Documentation/mainboard/starlabs/labtop_kbl.md b/Documentation/mainboard/starlabs/labtop_kbl.md new file mode 100644 index 0000000..4b9dfd9 --- /dev/null +++ b/Documentation/mainboard/starlabs/labtop_kbl.md @@ -0,0 +1,153 @@ +# Star Labs LabTop + +## Specs + +- CPU (full processor specs available at https://ark.intel.com) + - Intel i7-8550u (Kaby Lake Refresh) +- EC + - ITE IT8987E + - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys + - Battery + - Charger, using AC adapter or USB-C PD + - Suspend / resume +- GPU + - Intel UHD Graphics 620 + - GOP driver is recommended, VBT is provided + - eDP 13-inch 1920x1080 LCD + - HDMI video + - USB-C DisplayPort video +- Memory + - 8GB on-board +- Networking + - AX201 CNVi WiFi / Bluetooth soldered to PCBA (Comet Lake) + - 8265 PCIe WiFi / Bluetooth soldered to PCBA (Kaby Lake Refresh) +- Sound + - Realtek ALC256 + - Internal speakers + - Internal microphone + - Combined headphone / microphone 3.5-mm jack + - HDMI audio + - USB-C DisplayPort audio +- Storage + - M.2 PCIe SSD + - RTS5129 MicroSD card reader +- USB + - 1280x720 CCD camera + - USB 3.1 Gen 2 Type-C (left) + - USB 3.1 Gen 2 Type-A (left) + - USB 3.1 Gen 1 Type-A (right) + +## Building coreboot + +### Preliminaries + +Prior to building coreboot the following files are required: +* Intel Flash Descriptor file (descriptor.bin) +* Intel Management Engine firmware (me.bin) + +All Star Labs platforms: +- Splash screen image in Windows 3.1 BMP format (Logo.bmp) + +These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo. + +### Build + +The following commands will build a working image: + +```bash +make distclean +make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_kbl +make +``` + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Vendor | Gigadevice | ++---------------------+------------+ +| Model | 25Q128JVSQ | ++---------------------+------------+ +| Size | 8 MiB | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +| External flashing | no | ++---------------------+------------+ + +#### **Requirements:** + +* fwupd version 1.5.6 or later +* The battery must be charged to at least 30% +* The charger must be connected (either USB-C or DC Jack) +* BIOS Lock must be disabled +* Supported Linux distribution (Ubuntu 20.04 +, Linux Mint 20.1 + elementaryOS 6 +, Manjaro 21+) + +**fwupd 1.5.6 or later** +To check the version of **fwupd** you have installed, open a terminal window and enter the below command: + +``` +fwupdmgr --version +``` + +This will show the version number. **1.5.6** or greater will work. + +On Ubuntu 20.04, Ubuntu 20.10, Linux Mint 20.1 and elementaryOS 6, fwupd 1.5.6 can be installed from our PPA with the below terminal commands: + +``` +sudo add-apt-repository ppa:starlabs/ppa +sudo apt update +sudo apt install fwupd +``` + +On Manjaro: + +``` +sudo pacman -Sy fwupd-git flashrom-starlabs +``` + +Instructions for other distributions will be added once fwupd 1.5.6 is available. If you are not using one of the distributions listed above, it is possible to install coreboot using a Live USB. + +**Disable BIOS Lock** +BIOS Lock must be disabled when switching from the standard AMI (American Megatrends Inc.) firmware to coreboot. To disable BIOS Lock: + +1. Start with your LabTop turned off. Turn it on whilst holding the **F2** key to access the BIOS settings. +2. When the BIOS settings load, use the arrow keys to navigate to the advanced tab. Here you will see BIOS Lock. +3. Press `Enter` to change this setting from **Enabled** to **Disabled** + + + +4. Next, press the `F10` key to **Save & Exit** and then `Enter` to confirm. + +#### **Switching Branch** + +Switching branch refers to changing from AMI firmware to coreboot, or vice versa. + +First, check for new firmware files with the below terminal command: + +``` +fwupdmgr refresh --force +``` + +Then, to change branch, enter the below terminal command: + +``` +fwupdmgr switch-branch +``` + +You can then select which branch you would like to use, by typing in the corresponding number: + +You will be prompted to confirm, press `y` to continue or `n` to cancel. + +Once the switch has been completed, you will be prompted to restart. + + +The next reboot can take up to **5 minutes,** do not interrupt this process or disconnect the charger. Once the reboot is complete, that's it - you'll continue to receive updates for whichever branch you are using. + +You can switch branch at any time. diff --git a/src/mainboard/starlabs/labtop/Kconfig b/src/mainboard/starlabs/labtop/Kconfig index cd5fc91..01559eb 100644 --- a/src/mainboard/starlabs/labtop/Kconfig +++ b/src/mainboard/starlabs/labtop/Kconfig @@ -13,7 +13,16 @@ select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SYSTEM_TYPE_LAPTOP
-config BOARD_STARLABS_LABTOP_CML +# config BOARD_STARLABS_LABTOP_KBL + select BOARD_ROMSIZE_KB_8192 + select BOARD_STARLABS_LABTOP_SERIES + select HAVE_INTEL_PTT + select HAVE_SPD_IN_CBFS + select MAINBOARD_HAS_LIBGFXINIT + select SOC_INTEL_KABYLAKE + select SPI_FLASH_GIGADEVICE + +# config BOARD_STARLABS_LABTOP_CML select BOARD_ROMSIZE_KB_16384 select BOARD_STARLABS_LABTOP_SERIES select HAVE_INTEL_PTT @@ -22,7 +31,7 @@ select SOC_INTEL_COMETLAKE_1 select SPI_FLASH_WINBOND
-config BOARD_STARLABS_STARBOOK_TGL +# config BOARD_STARLABS_STARBOOK_TGL select BOARD_ROMSIZE_KB_16384 select BOARD_STARLABS_LABTOP_SERIES select DRIVERS_INTEL_USB4_RETIMER @@ -41,15 +50,18 @@ default "starlabs/labtop"
config VARIANT_DIR + default "kbl" if BOARD_STARLABS_LABTOP_KBL default "cml" if BOARD_STARLABS_LABTOP_CML default "tgl" if BOARD_STARLABS_STARBOOK_TGL
config MAINBOARD_PART_NUMBER + default "LabTop Mk III" if BOARD_STARLABS_LABTOP_KBL default "LabTop Mk IV" if BOARD_STARLABS_LABTOP_CML default "StarBook Mk V" if BOARD_STARLABS_STARBOOK_TGL
config MAINBOARD_FAMILY string + default "L3" if BOARD_STARLABS_LABTOP_KBL default "L4" if BOARD_STARLABS_LABTOP_CML default "B5" if BOARD_STARLABS_STARBOOK_TGL
diff --git a/src/mainboard/starlabs/labtop/Kconfig.name b/src/mainboard/starlabs/labtop/Kconfig.name index 32dfe0b..404b42e 100644 --- a/src/mainboard/starlabs/labtop/Kconfig.name +++ b/src/mainboard/starlabs/labtop/Kconfig.name @@ -1,7 +1,11 @@ comment "Star Labs LabTop Series"
+config BOARD_STARLABS_LABTOP_KBL + bool "Star Labs LabTop Mk III (i7-8550u)" + config BOARD_STARLABS_LABTOP_CML bool "Star Labs LabTop Mk IV (i3-10110u and i7-10710u)"
config BOARD_STARLABS_STARBOOK_TGL bool "Star Labs StarBook Mk V (i3-1115G4 and i7-1165G7)" + diff --git a/src/mainboard/starlabs/labtop/acpi/ec.asl b/src/mainboard/starlabs/labtop/acpi/ec.asl new file mode 100644 index 0000000..853b087 --- /dev/null +++ b/src/mainboard/starlabs/labtop/acpi/ec.asl @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ diff --git a/src/mainboard/starlabs/labtop/acpi/superio.asl b/src/mainboard/starlabs/labtop/acpi/superio.asl new file mode 100644 index 0000000..853b087 --- /dev/null +++ b/src/mainboard/starlabs/labtop/acpi/superio.asl @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ diff --git a/src/mainboard/starlabs/labtop/dsdt.asl b/src/mainboard/starlabs/labtop/dsdt.asl index e6ed8c9..c2544d0 100644 --- a/src/mainboard/starlabs/labtop/dsdt.asl +++ b/src/mainboard/starlabs/labtop/dsdt.asl @@ -18,20 +18,28 @@ { #include <acpi/dsdt_top.asl> #include <soc/intel/common/block/acpi/acpi/platform.asl> + + /* global NVS and variables */ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + /* CPU */ #include <cpu/intel/common/acpi/cpu.asl>
Device (_SB.PCI0) { -#if CONFIG(BOARD_STARLABS_LABTOP_CML) - /* Comet Lake */ - #include <soc/intel/common/block/acpi/acpi/northbridge.asl> - #include <soc/intel/cannonlake/acpi/southbridge.asl> -#elif CONFIG(BOARD_STARLABS_STARBOOK_TGL) +#if CONFIG(BOARD_STARLABS_STARBOOK_TGL) /* Tiger Lake */ #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/tigerlake/acpi/southbridge.asl> #include <soc/intel/tigerlake/acpi/tcss.asl> +#elif CONFIG(BOARD_STARLABS_LABTOP_CML) + /* Comet Lake */ + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/cannonlake/acpi/southbridge.asl> + /* Kaby Lake */ +#elif CONFIG(BOARD_STARLABS_LABTOP_KBL) + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> #endif
/* PS/2 Keyboard */ diff --git a/src/mainboard/starlabs/labtop/mainboard.c b/src/mainboard/starlabs/labtop/mainboard.c index 5ea0aae..bf53524 100644 --- a/src/mainboard/starlabs/labtop/mainboard.c +++ b/src/mainboard/starlabs/labtop/mainboard.c @@ -33,10 +33,12 @@
const char *smbios_system_sku(void) { - if (CONFIG(BOARD_STARLABS_LABTOP_CML)) - return "L4"; - else if (CONFIG(BOARD_STARLABS_STARBOOK_TGL)) + if (CONFIG(BOARD_STARLABS_STARBOOK_TGL)) return "B5"; + else if (CONFIG(BOARD_STARLABS_LABTOP_CML)) + return "L4"; + else if (CONFIG(BOARD_STARLABS_LABTOP_KBL)) + return "L3-U"; }
u8 smbios_mainboard_feature_flags(void) diff --git a/src/mainboard/starlabs/labtop/spd/spd.h b/src/mainboard/starlabs/labtop/spd/spd.h new file mode 100644 index 0000000..d334f88 --- /dev/null +++ b/src/mainboard/starlabs/labtop/spd/spd.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MAINBOARD_SPD_H_ +#define _MAINBOARD_SPD_H_ + +#include <gpio.h> + +void mainboard_fill_dq_map_data(void *dq_map_ptr); +void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); + +#endif diff --git a/src/mainboard/starlabs/labtop/spd/spd_util.c b/src/mainboard/starlabs/labtop/spd/spd_util.c new file mode 100644 index 0000000..b22ee91 --- /dev/null +++ b/src/mainboard/starlabs/labtop/spd/spd_util.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <string.h> + +#include "spd.h" + +void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = {121, 81, 100}; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + static const u16 RcompTarget[5] = {100, 40, 20, 20, 26}; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} diff --git a/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb b/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb index b1fd66a..6cdc775 100644 --- a/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb +++ b/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb @@ -161,7 +161,7 @@ end end device pci 1f.1 off end # P2SB - device pci 1f.2 hidden end # Power Management Controller + device pci 1f.2 hidden end # Power Management Controller device pci 1f.3 on # Intel HDA subsystemid 0x10ec 0x119e register "PchHdaAudioLinkHda" = "1" diff --git a/src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc b/src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc new file mode 100644 index 0000000..c00538b --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc @@ -0,0 +1,11 @@ +## SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR) + +bootblock-y += gpio.c + +romstage-y += romstage.c + +ramstage-y += devtree.c +ramstage-y += gpio.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/starlabs/labtop/variants/kbl/board.fmd b/src/mainboard/starlabs/labtop/variants/kbl/board.fmd new file mode 100644 index 0000000..08bc519 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/board.fmd @@ -0,0 +1,13 @@ +# +# Manually defined FMD in order to ensure that space is reserved for the EC +# at the top of the BIOS region. +# +FLASH 8M { + BIOS@0x200000 0x600000 { + RW_MRC_CACHE@0x0 0x10000 + SMMSTORE@0x10000 0x40000 + CONSOLE@0x50000 0x20000 + FMAP@0x70000 0x200 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/starlabs/labtop/variants/kbl/data.vbt b/src/mainboard/starlabs/labtop/variants/kbl/data.vbt new file mode 100644 index 0000000..12010f3 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/data.vbt Binary files differ diff --git a/src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb new file mode 100644 index 0000000..234432d --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb @@ -0,0 +1,171 @@ +chip soc/intel/skylake +# CPU + # Power limit + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 15, + }" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + + # Graphics + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "panel_cfg" = "{ + .up_delay_ms = 0, // T3 + .backlight_on_delay_ms = 0, // T7 + .backlight_off_delay_ms = 0, // T9 + .down_delay_ms = 0, // T10 + .cycle_delay_ms = 500, // T12 + .backlight_pwm_hz = 200, // PWM + }" + + # FSP Memory + register "SaGv" = "SaGv_Enabled" + +# FSP Silicon + # Serial I/O + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, + }" + + # Power + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "3" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + + # Thermal + register "tcc_offset" = "10" + + # PM Util + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_C" + register "gpe0_dw2" = "GPP_E" + + # Enable the correct decode ranges on the LPC bus. + register "lpc_ioe" = "LPC_IOE_EC_4E_4F | + LPC_IOE_KBC_60_64 | + LPC_IOE_EC_62_66" + +# Actual device tree. + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA Thermal Device + device pci 14.0 on # USB xHCI + # USB 2.0 Devices + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Motherboard USB Type C + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Motherboard USB 3.0 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Daughterboard USB 3.0 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Internal Webcam + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Daughterboard SD Card + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Internal Bluetooth + + # USB 3.0 Devices + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Motherboard USB Type C + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Motherboard USB 3.0 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Daughterboard USB 3.0 + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 on # I2C #0 + chip drivers/i2c/hid + register "generic.hid" = ""STAR0001"" + register "generic.desc" = ""Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device pci 15.1 off end # I2C1 + device pci 15.2 off end # I2C2 + device pci 15.3 off end # I2C3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on # SATA + register "SataSalpSupport" = "1" + # Port 1 + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[1]" = "1" + end + device pci 19.0 on end # UART #2 + device pci 19.1 off end # I2C4 + device pci 19.2 off end # I2C5 + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 on # PCI Express Port 6 (WLAN) + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "4" + register "PcieRpClkSrcNumber[5]" = "4" + register "PcieRpLtrEnable[5]" = "1" + chip drivers/wifi/generic + device generic 0 on end + end + end + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on # PCI Express Port 9(SSD x4) + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "0" + register "PcieRpClkSrcNumber[8]" = "0" + register "PcieRpLtrEnable[8]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" + end + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1e.4 off end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDCard + device pci 1f.0 on # LPC Interface + # LPC configuration from lspci -s 1f.0 -xxx + # Address 0x84: Decode 0x680 - 0x68F + register "gen1_dec" = "0x000c0681" + # Address 0x88: Decode + register "gen2_dec" = "0x000c1641" + # Address 0x8C: Decode 0x200 - 0x2FF + register "gen3_dec" = "0x00000069" + # Address 0x90: Decode 0x80 - 0x8F (Port 80) + register "gen4_dec" = "0x0000006d" + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + chip ec/starlabs/merlin + # Port 4Eh/4Fh + device pnp 4e.0 on # IO Interface + end + end + end + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + subsystemid 0x10ec 0x111e + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/starlabs/labtop/variants/kbl/devtree.c b/src/mainboard/starlabs/labtop/variants/kbl/devtree.c new file mode 100644 index 0000000..ecb65f3 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/devtree.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <chip.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <option.h> +#include <types.h> + +#include "baseboard/variants.h" + +struct device *variant_devtree_update(void) +{ + config_t *cfg = config_of_soc(); + struct soc_power_limits_config *soc_conf = &cfg->power_limits_config; + + /* Update PL2 based on CMOS settings */ + switch (get_uint_option("tdp", 0)) { + case 1: + soc_conf->tdp_pl1_override = 17; + soc_conf->tdp_pl2_override = 20; + break; + case 2: + soc_conf->tdp_pl1_override = 20; + soc_conf->tdp_pl2_override = 25; + break; + default: + soc_conf->tdp_pl1_override = 15; + soc_conf->tdp_pl2_override = 15; + break; + } + + /* Return the correct network device for this platform. */ + return pcidev_on_root(0x1c, 5); +} diff --git a/src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads b/src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads new file mode 100644 index 0000000..8402b39 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, -- USB-C + HDMI1, -- USB-C + HDMI2, -- HDMI + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/starlabs/labtop/variants/kbl/gpio.c b/src/mainboard/starlabs/labtop/variants/kbl/gpio.c new file mode 100644 index 0000000..f60ba0f --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/gpio.c @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "baseboard/variants.h" + +/* + * All definitions are taken from a comparison of the output of "inteltool -a" + * using the stock BIOS and with coreboot. + */ + +/* Early pad configuration in romstage. */ +const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Pad configuration in ramstage. */ +const struct pad_config gpio_table[] = { + PAD_CFG_NF(GPD0, NONE, PWROK, NF1), + PAD_CFG_NF(GPD1, NONE, PWROK, NF1), + _PAD_CFG_STRUCT(GPD2, 0x04000300, 0x1000), + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + _PAD_CFG_STRUCT(GPD7, 0x04000101, 0x1000), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_CFG_GPI(GPD9, DN_20K, PWROK), + PAD_CFG_NF(GPD10, DN_20K, PWROK, NF1), + PAD_CFG_NF(GPD11, DN_20K, PWROK, NF1), + PAD_NC(GPP_A0, NONE), + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_NC(GPP_A7, NONE), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + PAD_NC(GPP_A10, DN_20K), + PAD_CFG_GPI(GPP_A11, DN_20K, DEEP), + PAD_NC(GPP_A12, NONE), + PAD_NC(GPP_A13, DN_20K), + PAD_NC(GPP_A14, DN_20K), + PAD_NC(GPP_A15, DN_20K), + PAD_NC(GPP_A16, DN_20K), + PAD_NC(GPP_A17, DN_20K), + PAD_NC(GPP_A18, DN_20K), + PAD_NC(GPP_A19, DN_20K), + PAD_NC(GPP_A20, DN_20K), + PAD_NC(GPP_A21, DN_20K), + PAD_NC(GPP_A22, DN_20K), + PAD_NC(GPP_A23, DN_20K), + PAD_NC(GPP_B0, DN_20K), + PAD_NC(GPP_B1, DN_20K), + PAD_NC(GPP_B2, DN_20K), + PAD_NC(GPP_B3, DN_20K), + PAD_CFG_TERM_GPO(GPP_B4, 1, UP_20K, DEEP), + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + PAD_CFG_GPI(GPP_B6, DN_20K, DEEP), + PAD_CFG_NF(GPP_B7, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_B8, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B10, DN_20K, DEEP, NF1), + PAD_NC(GPP_B11, DN_20K), + PAD_NC(GPP_B12, DN_20K), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_NC(GPP_B14, DN_20K), + PAD_NC(GPP_B15, DN_20K), + PAD_NC(GPP_B16, DN_20K), + PAD_NC(GPP_B17, DN_20K), + PAD_NC(GPP_B18, DN_20K), + PAD_NC(GPP_B19, DN_20K), + PAD_NC(GPP_B20, DN_20K), + PAD_NC(GPP_B21, DN_20K), + PAD_NC(GPP_B22, DN_20K), + PAD_NC(GPP_B23, DN_20K), + PAD_CFG_NF(GPP_C0, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_C1, UP_20K, DEEP, NF1), + PAD_NC(GPP_C2, DN_20K), + PAD_NC(GPP_C3, DN_20K), + PAD_NC(GPP_C4, DN_20K), + PAD_NC(GPP_C5, DN_20K), + PAD_NC(GPP_C6, DN_20K), + PAD_NC(GPP_C7, DN_20K), + PAD_CFG_NF(GPP_C8, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_C9, UP_20K, DEEP, NF1), + _PAD_CFG_STRUCT(GPP_C10, 0x44000301, 0x3000), + PAD_CFG_NF(GPP_C11, UP_20K, DEEP, NF1), + PAD_NC(GPP_C12, UP_20K), + PAD_NC(GPP_C13, UP_20K), + PAD_NC(GPP_C14, UP_20K), + PAD_NC(GPP_C15, UP_20K), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + PAD_NC(GPP_C22, NONE), + _PAD_CFG_STRUCT(GPP_C23, 0x80100100, 0x3000), + PAD_NC(GPP_D0, DN_20K), + PAD_NC(GPP_D1, DN_20K), + PAD_NC(GPP_D2, DN_20K), + PAD_NC(GPP_D3, DN_20K), + PAD_NC(GPP_D4, DN_20K), + PAD_NC(GPP_D5, DN_20K), + PAD_NC(GPP_D6, DN_20K), + PAD_NC(GPP_D7, DN_20K), + PAD_NC(GPP_D8, DN_20K), + PAD_NC(GPP_D9, DN_20K), + PAD_NC(GPP_D10, DN_20K), + PAD_NC(GPP_D11, DN_20K), + PAD_NC(GPP_D12, DN_20K), + PAD_NC(GPP_D13, DN_20K), + PAD_NC(GPP_D14, DN_20K), + PAD_NC(GPP_D15, DN_20K), + PAD_NC(GPP_D16, DN_20K), + PAD_NC(GPP_D17, DN_20K), + PAD_NC(GPP_D18, DN_20K), + PAD_NC(GPP_D19, DN_20K), + PAD_CFG_TERM_GPO(GPP_D20, 1, UP_20K, DEEP), + PAD_NC(GPP_D21, DN_20K), + PAD_NC(GPP_D22, DN_20K), + PAD_NC(GPP_D23, DN_20K), + PAD_NC(GPP_E0, DN_20K), + PAD_NC(GPP_E1, DN_20K), + _PAD_CFG_STRUCT(GPP_E2, 0x44000601, 0x0000), + PAD_NC(GPP_E3, DN_20K), + PAD_NC(GPP_E4, DN_20K), + PAD_NC(GPP_E5, DN_20K), + PAD_CFG_NF(GPP_E6, NONE, PWROK, NF1), + PAD_NC(GPP_E7, DN_20K), + PAD_NC(GPP_E8, DN_20K), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + PAD_NC(GPP_E12, DN_20K), + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + _PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0000), + _PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0000), + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), + PAD_NC(GPP_E20, DN_20K), + PAD_NC(GPP_E21, DN_20K), + PAD_NC(GPP_E22, DN_20K), + PAD_NC(GPP_E23, DN_20K), + PAD_NC(GPP_F0, DN_20K), + PAD_NC(GPP_F1, DN_20K), + PAD_NC(GPP_F2, DN_20K), + PAD_NC(GPP_F3, DN_20K), + PAD_NC(GPP_F4, DN_20K), + PAD_NC(GPP_F5, DN_20K), + PAD_NC(GPP_F6, DN_20K), + PAD_NC(GPP_F7, DN_20K), + PAD_CFG_NF(GPP_F8, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_F9, DN_20K, DEEP, NF1), + PAD_NC(GPP_F10, DN_20K), + PAD_NC(GPP_F11, DN_20K), + PAD_NC(GPP_F12, DN_20K), + PAD_NC(GPP_F13, DN_20K), + PAD_NC(GPP_F14, DN_20K), + PAD_NC(GPP_F15, DN_20K), + PAD_NC(GPP_F16, DN_20K), + PAD_NC(GPP_F17, DN_20K), + PAD_NC(GPP_F18, DN_20K), + PAD_NC(GPP_F19, DN_20K), + PAD_NC(GPP_F20, DN_20K), + PAD_NC(GPP_F21, DN_20K), + PAD_NC(GPP_F22, DN_20K), + PAD_NC(GPP_F23, DN_20K), + PAD_CFG_GPI(GPP_G0, DN_20K, DEEP), + PAD_CFG_GPI(GPP_G1, DN_20K, DEEP), + PAD_CFG_GPI(GPP_G2, DN_20K, DEEP), + PAD_CFG_GPI(GPP_G3, DN_20K, DEEP), + PAD_CFG_GPI(GPP_G4, DN_20K, DEEP), + PAD_CFG_GPI(GPP_G5, DN_20K, DEEP), + PAD_CFG_GPI(GPP_G6, DN_20K, DEEP), + PAD_CFG_GPI(GPP_G7, DN_20K, DEEP), + +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/starlabs/labtop/variants/kbl/hda_verb.c b/src/mainboard/starlabs/labtop/variants/kbl/hda_verb.c new file mode 100644 index 0000000..7a0ea24 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/hda_verb.c @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269 + 0xffffffff, // Subsystem ID + 16, // Number of jacks (NID entries) + + /* Reset Codec First */ + AZALIA_RESET(0x1), + + /* HDA Codec Subsystem ID Verb-table */ + AZALIA_SUBVENDOR(0, 0x10EC111E), + + /* Pin Widget Verb-table */ + AZALIA_PIN_CFG(0, 0x01, 0x00000000), + AZALIA_PIN_CFG(0, 0x12, 0x90a61120), + AZALIA_PIN_CFG(0, 0x14, 0x90171110), + AZALIA_PIN_CFG(0, 0x15, 0x042B1010), + AZALIA_PIN_CFG(0, 0x17, 0x411111F0), + AZALIA_PIN_CFG(0, 0x18, 0x04AB1020), + AZALIA_PIN_CFG(0, 0x19, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1A, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1B, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1D, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1E, 0x411111F0), + + /* Widget node 0x20 */ + 0x02050018, + 0x02040184, /* Stock: 0x02043984 */ + 0x0205001C, + 0x02040800, + + /* Widget node 0x20 - 1 */ + 0x02050024, + 0x02040000, + 0x02050004, + 0x02040080, + + /* Widget node 0x20 - 2 */ + 0x02050008, + 0x02040300, + 0x0205000C, + 0x02043F00, + + /* Widget node 0x20 - 3 */ + 0x02050015, + 0x02048002, + 0x02050015, + 0x02048002, + + /* Widget node 0x0C */ + 0x00C37080, + 0x00270610, + 0x00D37080, + 0x00370610, + + /* + * Equalizer: + * + * AGC + * Threshold: - 6.00 dB + * Front Boost: + 6.00 dB + * Post Boost: + 6.00 dB + * + * Low Pass Filter + * Boost Gain: Enabled + * BW: 200Hz + * Gain: + 4.00 dB + * + * Band Pass Filter 1 + * Fc: 240Hz + * BW: 400Hz + * Gain: + 6.00 dB + * + * Band Pass Filter 2 + * Fc: 16000Hz + * BW: 1000Hz + * Gain: - 12.00 dB + * + * High Pass Filter + * Boost Gain: Enabled + * BW: 200Hz + * Gain: - 4.00 dB + * + * Class D Amp + * Power: 2.5W + * Resistance: 4ohms + * + * EQ Output + * Left: + 3.00 dB + * Right: + 3.00 dB + * + * VARQ + * Q: 0.707 + */ + + 0x05350000, + 0x0534065A, + 0x0535001d, + 0x05340800, + + 0x0535001e, + 0x05340B4C, + 0x05350003, + 0x05341F7A, + + 0x05350004, + 0x0534FA18, + 0x0535000F, + 0x05341961, + + 0x05350010, + 0x053412C2, + 0x05350011, + 0x0534F405, + + 0x05350018, + 0x0534C1AA, + 0x05350019, + 0x05341E5E, + + 0x0535001A, + 0x05340FED, + 0x0535001B, + 0x05341F2C, + + 0x0535001C, + 0x0534095C, + 0x05450000, + 0x05440000, + + 0x0545001d, + 0x05440800, + 0x0545001e, + 0x05440B4C, + + 0x05450003, + 0x05441F7A, + 0x05450004, + 0x0544FA18, + + 0x0545000F, + 0x05441961, + 0x05450010, + 0x054412C2, + + 0x05450011, + 0x0544F405, + 0x05450018, + 0x0544C1AA, + + 0x05450019, + 0x05441E5E, + 0x0545001A, + 0x05440FED, + + 0x0545001B, + 0x05441F2C, + 0x0545001C, + 0x0544095C, + + 0x05350000, + 0x0534465A, + 0x02050038, + 0x02044901, + + 0x02050013, + 0x02044193, + 0x02050016, + 0x02044E50, + + 0x02050012, + 0x0204EBC4, + 0x02050020, + 0x020451FF, + + 0x8086280b, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(2, 0x80860101), + + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/starlabs/labtop/variants/kbl/romstage.c b/src/mainboard/starlabs/labtop/variants/kbl/romstage.c new file mode 100644 index 0000000..28b59e17 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/romstage.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <console/console.h> +#include <ec/acpi/ec.h> +#include <option.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include <stdint.h> +#include <types.h> + +#include "spd/spd_util.c" +#include "spd/spd.h" + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + + /* Use the correct entry in the SPD table defined in Makefile.inc */ + u8 spd_index = 6; + printk(BIOS_INFO, "SPD index %d\n", spd_index); + + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + /* struct region_device spd_rdev; */ + + mem_cfg->DqPinsInterleaved = 0; + mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; + mem_cfg->MemorySpdPtr00 = spd_cbfs_map(spd_index); + if (!mem_cfg->MemorySpdPtr00) + die("spd.bin not found\n"); + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; + + mupd->FspmTestConfig.DmiVc1 = 1; + + const uint8_t ht = get_uint_option("hyper_threading", + mupd->FspmConfig.HyperThreading); + mupd->FspmConfig.HyperThreading = ht; +}