[coreboot-gerrit] Change in libgfxinit[master]: gfx gma skylake: Implement some workarounds

[Nico Huber (Code Review)]

Nico Huber has submitted this change. ( https://review.coreboot.org/c/libgfxinit/+/46635 )

Change subject: gfx gma skylake: Implement some workarounds
......................................................................

gfx gma skylake: Implement some workarounds

Without these workarounds, gfx_test will leave a WHL-U Librem Mini v1 in
a state where entering low-power states results in a hang. With these
workarounds, the system no longer locks up after running gfx_test. Looks
like the hang does not happen when coreboot runs libgfxinit.

Steps to reproduce the hang:
- Boot Linux without loading i915.
- Run gfx_test without the workarounds.
- After gfx_test exits and the machine enters a low-power state,
  it will lock up.

If something keeps the CPU from getting into low-power states (e.g.
`cat /dev/zero > /dev/null`), the machine will not lock up. However,
stopping the load task after gfx_test has run will result in a lock-up.

Change-Id: I4cd64cf4c1e702dc05709adc345a976a4e3c1ded
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/46635
Reviewed-by: Nico Huber 
---
M common/hw-gfx-gma-registers.ads
M common/skylake/hw-gfx-gma-power_and_clocks.adb
2 files changed, 14 insertions(+), 0 deletions(-)

Approvals:
  Angel Pons: Verified
  Nico Huber: Looks good to me, approved

diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads
index 68e5664..3318ab1 100644
--- a/common/hw-gfx-gma-registers.ads
+++ b/common/hw-gfx-gma-registers.ads
@@ -144,6 +144,7 @@
       TRANSC_CLK_SEL,
       CDCLK_FREQ,
       NDE_RSTWRN_OPT,
+      GEN8_CHICKEN_DCPR_1,
       BLC_PWM_CPU_CTL2,
       BLC_PWM_CPU_CTL,
       DFSM,
@@ -1489,6 +1490,7 @@
       ARB_CTL               => 16#04_5000# / Register_Width,
       DBUF_CTL              => 16#04_5008# / Register_Width,
       NDE_RSTWRN_OPT        => 16#04_6408# / Register_Width,
+      GEN8_CHICKEN_DCPR_1   => 16#04_6430# / Register_Width,
       PCH_DREF_CONTROL      => 16#0c_6200# / Register_Width,
       PCH_DPLL_SEL          => 16#0c_7000# / Register_Width,
       GT_MAILBOX            => 16#13_8124# / Register_Width,
diff --git a/common/skylake/hw-gfx-gma-power_and_clocks.adb b/common/skylake/hw-gfx-gma-power_and_clocks.adb
index edbaf00..ec71359 100644
--- a/common/skylake/hw-gfx-gma-power_and_clocks.adb
+++ b/common/skylake/hw-gfx-gma-power_and_clocks.adb
@@ -82,6 +82,8 @@
    LCPLL1_CTL_PLL_ENABLE               : constant := 1 * 2 ** 31;
    LCPLL1_CTL_PLL_LOCK                 : constant := 1 * 2 ** 30;

+   DISP_FBC_MEMORY_WAKE                : constant := 1 * 2 ** 31;
+
    ----------------------------------------------------------------------------

CDCLK_CTL_CD_FREQ_SELECT_MASK       : constant := 3 * 2 ** 26;
@@ -351,6 +353,16 @@
         (Register    => Registers.LCPLL1_CTL,
          Mask        => LCPLL1_CTL_PLL_LOCK);

+      -- WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl
+      Registers.Set_Mask
+        (Register    => Registers.GEN8_CHICKEN_DCPR_1,
+         Mask        => 1 * 2 ** 13);
+
+      -- Display WA #0859 WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl
+      Registers.Set_Mask
+        (Register    => Registers.ARB_CTL,
+         Mask        => DISP_FBC_MEMORY_WAKE);
+
       Get_Cur_CDClk (Config.CDClk);
       Get_Max_CDClk (Config.Max_CDClk);
       Set_CDClk (Config.Default_CDClk_Freq);