Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40291 )
Change subject: vendorcode/amd/agesa/.../Mem/Tech/DDR3: XMP memory profiles support ......................................................................
vendorcode/amd/agesa/.../Mem/Tech/DDR3: XMP memory profiles support
Experimental XMP support which will be tested ASAP on f15tn and f16kb. Added using the datasheets from https://github.com/mikebdp2/ddr3spd
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I0dac8b317a9413172f603c543ab005a377e4ce03 --- M src/vendorcode/amd/Kconfig A src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h 5 files changed, 264 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/40291/1
diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig index 3e3a0e9..5291a9c 100644 --- a/src/vendorcode/amd/Kconfig +++ b/src/vendorcode/amd/Kconfig @@ -46,6 +46,10 @@ source "src/vendorcode/amd/pi/Kconfig" endif
+if CPU_AMD_AGESA_OPENSOURCE +source "src/vendorcode/amd/agesa/Kconfig" +endif + config AGESA_EXTRA_TIMESTAMPS bool "Add instrumentation for AGESA calls" default n diff --git a/src/vendorcode/amd/agesa/Kconfig b/src/vendorcode/amd/agesa/Kconfig new file mode 100644 index 0000000..dcfa722 --- /dev/null +++ b/src/vendorcode/amd/agesa/Kconfig @@ -0,0 +1,44 @@ +# +# This file is part of the coreboot project. +# +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if CPU_AMD_AGESA_FAMILY14 || CPU_AMD_AGESA_FAMILY15_TN || CPU_AMD_AGESA_FAMILY16_KB + +choice + prompt "DDR3 memory profile" + default CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC + help + Choose the DDR3 memory profile to use for your RAM sticks, i.e. XMP 1. + + XMP support is experimental, and your PC will fail booting if you choose + a profile which does not exist at ANY of your RAM sticks! If in doubt, + check their SPD Data using a coreboot's fork of memtest86+ 5.01. + +config CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC + bool "JEDEC" + help + JEDEC memory profile, standard and stable. Is guaranteed to be working. + +config CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1 + bool "XMP 1" + help + XMP 1 memory profile. Check that it exists at ALL of your RAM sticks! + +config CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2 + bool "XMP 2" + help + XMP 2 memory profile. Check that it exists at ALL of your RAM sticks! + +endchoice + +endif diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h index 3b37429..bd4c372 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h @@ -95,6 +95,9 @@
#define SPD_FTB 9
+#ifdef CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC + #if CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC == TRUE + #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11
@@ -103,18 +106,75 @@ #define SPD_CASHI 15 #define SPD_TAA 16
-#define SPD_TRP 20 -#define SPD_TRRD 19 -#define SPD_TRCD 18 -#define SPD_TRAS 22 #define SPD_TWR 17 -#define SPD_TWTR 26 -#define SPD_TRTP 27 -#define SPD_TRC 23 +#define SPD_TRCD 18 +#define SPD_TRRD 19 +#define SPD_TRP 20 #define SPD_UPPER_TRC 21 /* bit 7:4 */ #define SPD_UPPER_TRAS 21 /* bit 3:0 */ -#define SPD_TFAW 29 +#define SPD_TRAS 22 +#define SPD_TRC 23 +#define SPD_TWTR 26 +#define SPD_TRTP 27 #define SPD_UPPER_TFAW 28 /* bit 3:0 */ +#define SPD_TFAW 29 + + #endif +#endif + +#ifdef CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1 + #if CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1 == TRUE + +#define SPD_DIVIDENT 180 +#define SPD_DIVISOR 181 + +#define SPD_TCK 186 +#define SPD_CASLO 188 +#define SPD_CASHI 189 +#define SPD_TAA 187 + +#define SPD_TWR 193 +#define SPD_TRCD 192 +#define SPD_TRRD 202 +#define SPD_TRP 191 +#define SPD_UPPER_TRC 194 /* bit 7:4 */ +#define SPD_UPPER_TRAS 194 /* bit 3:0 */ +#define SPD_TRAS 195 +#define SPD_TRC 196 +#define SPD_TWTR 205 +#define SPD_TRTP 201 +#define SPD_UPPER_TFAW 203 /* bit 3:0 */ +#define SPD_TFAW 204 + + #endif +#endif + +#ifdef CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2 + #if CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2 == TRUE + +#define SPD_DIVIDENT 182 +#define SPD_DIVISOR 183 + +#define SPD_TCK 221 +#define SPD_CASLO 223 +#define SPD_CASHI 224 +#define SPD_TAA 222 + +#define SPD_TWR 228 +#define SPD_TRCD 227 +#define SPD_TRRD 237 +#define SPD_TRP 226 +#define SPD_UPPER_TRC 229 /* bit 7:4 */ +#define SPD_UPPER_TRAS 229 /* bit 3:0 */ +#define SPD_TRAS 230 +#define SPD_TRC 231 +#define SPD_TWTR 240 +#define SPD_TRTP 236 +#define SPD_UPPER_TFAW 238 /* bit 3:0 */ +#define SPD_TFAW 239 + + #endif +#endif
#define SPD_TCK_FTB 34 #define SPD_TAA_FTB 35 diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h index ab46e4a..058eead 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h @@ -94,6 +94,9 @@
#define SPD_FTB 9
+#ifdef CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC + #if CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC == TRUE + #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11
@@ -102,18 +105,75 @@ #define SPD_CASHI 15 #define SPD_TAA 16
-#define SPD_TRP 20 -#define SPD_TRRD 19 -#define SPD_TRCD 18 -#define SPD_TRAS 22 #define SPD_TWR 17 -#define SPD_TWTR 26 -#define SPD_TRTP 27 -#define SPD_TRC 23 +#define SPD_TRCD 18 +#define SPD_TRRD 19 +#define SPD_TRP 20 #define SPD_UPPER_TRC 21 /* bit 7:4 */ #define SPD_UPPER_TRAS 21 /* bit 3:0 */ -#define SPD_TFAW 29 +#define SPD_TRAS 22 +#define SPD_TRC 23 +#define SPD_TWTR 26 +#define SPD_TRTP 27 #define SPD_UPPER_TFAW 28 /* bit 3:0 */ +#define SPD_TFAW 29 + + #endif +#endif + +#ifdef CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1 + #if CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1 == TRUE + +#define SPD_DIVIDENT 180 +#define SPD_DIVISOR 181 + +#define SPD_TCK 186 +#define SPD_CASLO 188 +#define SPD_CASHI 189 +#define SPD_TAA 187 + +#define SPD_TWR 193 +#define SPD_TRCD 192 +#define SPD_TRRD 202 +#define SPD_TRP 191 +#define SPD_UPPER_TRC 194 /* bit 7:4 */ +#define SPD_UPPER_TRAS 194 /* bit 3:0 */ +#define SPD_TRAS 195 +#define SPD_TRC 196 +#define SPD_TWTR 205 +#define SPD_TRTP 201 +#define SPD_UPPER_TFAW 203 /* bit 3:0 */ +#define SPD_TFAW 204 + + #endif +#endif + +#ifdef CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2 + #if CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2 == TRUE + +#define SPD_DIVIDENT 182 +#define SPD_DIVISOR 183 + +#define SPD_TCK 221 +#define SPD_CASLO 223 +#define SPD_CASHI 224 +#define SPD_TAA 222 + +#define SPD_TWR 228 +#define SPD_TRCD 227 +#define SPD_TRRD 237 +#define SPD_TRP 226 +#define SPD_UPPER_TRC 229 /* bit 7:4 */ +#define SPD_UPPER_TRAS 229 /* bit 3:0 */ +#define SPD_TRAS 230 +#define SPD_TRC 231 +#define SPD_TWTR 240 +#define SPD_TRTP 236 +#define SPD_UPPER_TFAW 238 /* bit 3:0 */ +#define SPD_TFAW 239 + + #endif +#endif
#define SPD_TCK_FTB 34 #define SPD_TAA_FTB 35 diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h index bf13c7f..da9d09f 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h @@ -95,6 +95,9 @@
#define SPD_FTB 9
+#ifdef CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC + #if CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC == TRUE + #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11
@@ -103,18 +106,87 @@ #define SPD_CASHI 15 #define SPD_TAA 16
-#define SPD_TRP 20 -#define SPD_TRRD 19 -#define SPD_TRCD 18 -#define SPD_TRAS 22 #define SPD_TWR 17 -#define SPD_TWTR 26 -#define SPD_TRTP 27 -#define SPD_TRC 23 +#define SPD_TRCD 18 +#define SPD_TRRD 19 +#define SPD_TRP 20 #define SPD_UPPER_TRC 21 /* bit 7:4 */ #define SPD_UPPER_TRAS 21 /* bit 3:0 */ -#define SPD_TFAW 29 +#define SPD_TRAS 22 +#define SPD_TRC 23 + +#define SPD_TRFC_LO 24 +#define SPD_TRFC_HI 25 + +#define SPD_TWTR 26 +#define SPD_TRTP 27 #define SPD_UPPER_TFAW 28 /* bit 3:0 */ +#define SPD_TFAW 29 + + #endif +#endif + +#ifdef CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1 + #if CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1 == TRUE + +#define SPD_DIVIDENT 180 +#define SPD_DIVISOR 181 + +#define SPD_TCK 186 +#define SPD_CASLO 188 +#define SPD_CASHI 189 +#define SPD_TAA 187 + +#define SPD_TWR 193 +#define SPD_TRCD 192 +#define SPD_TRRD 202 +#define SPD_TRP 191 +#define SPD_UPPER_TRC 194 /* bit 7:4 */ +#define SPD_UPPER_TRAS 194 /* bit 3:0 */ +#define SPD_TRAS 195 +#define SPD_TRC 196 + +#define SPD_TRFC_LO 199 +#define SPD_TRFC_HI 200 + +#define SPD_TWTR 205 +#define SPD_TRTP 201 +#define SPD_UPPER_TFAW 203 /* bit 3:0 */ +#define SPD_TFAW 204 + + #endif +#endif + +#ifdef CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2 + #if CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2 == TRUE + +#define SPD_DIVIDENT 182 +#define SPD_DIVISOR 183 + +#define SPD_TCK 221 +#define SPD_CASLO 223 +#define SPD_CASHI 224 +#define SPD_TAA 222 + +#define SPD_TWR 228 +#define SPD_TRCD 227 +#define SPD_TRRD 237 +#define SPD_TRP 226 +#define SPD_UPPER_TRC 229 /* bit 7:4 */ +#define SPD_UPPER_TRAS 229 /* bit 3:0 */ +#define SPD_TRAS 230 +#define SPD_TRC 231 + +#define SPD_TRFC_LO 234 +#define SPD_TRFC_HI 235 + +#define SPD_TWTR 240 +#define SPD_TRTP 236 +#define SPD_UPPER_TFAW 238 /* bit 3:0 */ +#define SPD_TFAW 239 + + #endif +#endif
#define SPD_TCK_FTB 34 #define SPD_TAA_FTB 35 @@ -122,9 +194,6 @@ #define SPD_TRP_FTB 37 #define SPD_TRC_FTB 38
-#define SPD_TRFC_LO 24 -#define SPD_TRFC_HI 25 - /*----------------------------- * Jedec DDR II related equates *-----------------------------