[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Pass more SPI options to FSP.

[Aaron Durbin (Code Review)]

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32791 )

Change subject: soc/intel/cannonlake: Pass more SPI options to FSP.
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Patch Set 2:

(1 comment)

https://review.coreboot.org/#/c/32791/2/src/soc/intel/cannonlake/chip.h 
File src/soc/intel/cannonlake/chip.h:

https://review.coreboot.org/#/c/32791/2/src/soc/intel/cannonlake/chip.h@41 
PS2, Line 41: #define SOC_INTEL_CML_SPI_DEV_MAX 3
> CsPolarity and CsEnable are 2-field arrays where each field indicates each Chip select i.e. […]

I see. They are controller based. Why aren't we grouping our options (chip.h) into a controller orientated format so it's clearer? We don't have to mirror the decisions in the UPD header. Similarly, PchSerialIoSpiMAX is a terrible name and doesn't convey what it's trying to represent. That is clearly an Intel name -- why carry over the confusion?