[coreboot-gerrit] [M] Change in coreboot[master]: spd.h: Move enum ddr3_module_type to ddr3.h

[Angel Pons (Code Review)]

Attention is currently required from: Jakub Czapiga, Elyes Haouas.

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71547 )

Change subject: spd.h: Move enum ddr3_module_type to ddr3.h
......................................................................

Patch Set 2: Code-Review+1

(2 comments)

File src/device/dram/ddr3.c:

https://review.coreboot.org/c/coreboot/+/71547/comment/c1e99edc_f2edbb11 
PS2, Line 537: switch (info->dimm_type) {
             : 		case SPD_DDR3_DIMM_TYPE_SO_DIMM:
             : 			dimm->mod_type = DDR3_SPD_SODIMM;
             : 			break;
             : 		case SPD_DDR3_DIMM_TYPE_72B_SO_CDIMM:
             : 			dimm->mod_type = DDR3_SPD_72B_SO_CDIMM;
             : 			break;
             : 		case SPD_DDR3_DIMM_TYPE_72B_SO_RDIMM:
             : 			dimm->mod_type = DDR3_SPD_72B_SO_RDIMM;
             : 			break;
             : 		case SPD_DDR3_DIMM_TYPE_UDIMM:
             : 			dimm->mod_type = DDR3_SPD_UDIMM;
             : 			break;
             : 		case SPD_DDR3_DIMM_TYPE_RDIMM:
             : 			dimm->mod_type = DDR3_SPD_RDIMM;
             : 			break;
             : 		case SPD_DDR3_DIMM_TYPE_UNDEFINED:
             : 		default:
             : 			dimm->mod_type = SPD_UNDEFINED;
             : 			break;
             : 		}
This catches invalid SPD types and replaces them with an "undefined" value. The new approach is simpler but doesn't do this. It doesn't seem to be a big deal anyway.

The bus width being hardcoded to 64 is more of a problem, actually.

File src/northbridge/intel/haswell/haswell_mrc/raminit.c:

https://review.coreboot.org/c/coreboot/+/71547/comment/fe58466c_e81d0b61 
PS2, Line 264: 				dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM;
Reminds us that this shouldn't be hardcoded