Marc Jones has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45270 )
Change subject: soc/intel/xeon_sp/skx: Update ITSS OperationRegion to ACPI2.0 notation ......................................................................
soc/intel/xeon_sp/skx: Update ITSS OperationRegion to ACPI2.0 notation
Prepare for merge with cpx. Use the C style operators instead of the ACPI1.x polish notation. This is much easier to read and matches the cpx code.
This generates the same ASL code. Checked with BUILD_TIMELESS on TiogaPass.
Change-Id: Id44138894d2ffed4c93afe5d4bbb4d59b538b577 Signed-off-by: Marc Jones marcjones@sysproconsulting.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/45270 Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Jay Talbott JayTalbott@sysproconsulting.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl 1 file changed, 2 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Jay Talbott: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl b/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl index dcb6fe2..b2a2ebf 100644 --- a/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl +++ b/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl @@ -8,10 +8,8 @@ * PIRQ routing control is in PCR ITSS region. */
-OperationRegion (ITSS, SystemMemory, - Add (PCR_ITSS_PIRQA_ROUT, - Add (CONFIG_PCR_BASE_ADDRESS, - ShiftLeft (PID_ITSS, PCR_PORTID_SHIFT))), 8) +OperationRegion (ITSS, SystemMemory, PCR_ITSS_PIRQA_ROUT + + CONFIG_PCR_BASE_ADDRESS + (PID_ITSS << PCR_PORTID_SHIFT), 8) Field (ITSS, ByteAcc, NoLock, Preserve) { PIRA, 8, /* PIRQA Routing Control */