[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake/bootblock: Do initial SoC commit till bootblock

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36550 )

Change subject: soc/intel/tigerlake/bootblock: Do initial SoC commit till bootblock
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Patch Set 9:

(3 comments)

https://review.coreboot.org/c/coreboot/+/36550/6/src/soc/intel/tigerlake/boo... 
File src/soc/intel/tigerlake/bootblock/pch.c:

https://review.coreboot.org/c/coreboot/+/36550/6/src/soc/intel/tigerlake/boo... 
PS6, Line 110: 	uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
> https://github. […]

there are 2 register one over PCR to provide decode range and another over primary config using PCI write

hence both programming are required

https://review.coreboot.org/c/coreboot/+/36550/9/src/soc/intel/tigerlake/boo... 
File src/soc/intel/tigerlake/bootblock/pch.c:

https://review.coreboot.org/c/coreboot/+/36550/9/src/soc/intel/tigerlake/boo... 
PS9, Line 106: 0xFFFFFFFF
> use lower case.

Done

https://review.coreboot.org/c/coreboot/+/36550/9/src/soc/intel/tigerlake/boo... 
File src/soc/intel/tigerlake/bootblock/report_platform.c:

https://review.coreboot.org/c/coreboot/+/36550/9/src/soc/intel/tigerlake/boo... 
PS9, Line 40: static uint8_t get_dev_revision(pci_devfn_t dev)
            : {
            : 	return pci_read_config8(dev, PCI_REVISION_ID);
            : }
            : 
            : static uint16_t get_dev_id(pci_devfn_t dev)
            : {
            : 	return pci_read_config16(dev, PCI_DEVICE_ID);
            : }
> static inline?

Done