Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35902 )
Change subject: soc/intel: apl,skl,cnl,icl: implement a PRMRR size selection algorithm
......................................................................
Patch Set 13:
(2 comments)
This change is ready for review.
https://review.coreboot.org/c/coreboot/+/35902/7//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/35902/7//COMMIT_MSG@34
PS7, Line 34: Todo: needs testing
I'm rather sure the alignment is 256MiB for newer SoCs. Maybe […]
The msr was 0xe1, which is 128-32 MiB and 1 MiB; I tested, 256 which leads to a hang on payload call
https://review.coreboot.org/c/coreboot/+/35902/4/src/soc/intel/common/block/...
File src/soc/intel/common/block/cpu/cpulib.c:
https://review.coreboot.org/c/coreboot/+/35902/4/src/soc/intel/common/block/...
PS4, Line 334: <<
not convinced. I would aggree for any other operator, but not for shift. […]
Done
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