Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu.
Hello Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80795?usp=email
to look at the new patch set (#4).
The following approvals got outdated and were removed: Code-Review+2 by Arthur Heymans, Verified+1 by build bot (Jenkins)
Change subject: soc/intel/xeon_sp: Drop SPI_BASE_ADDRESS from _CRS ......................................................................
soc/intel/xeon_sp: Drop SPI_BASE_ADDRESS from _CRS
Drop SPI_BASE_ADDRESS from _CRS since this address is just a regular PCI BAR on the FASTSPI PCI device. Currently the PCI device is always visible and thus doesn't need special care in the host-bridge _CRS.
In case the PCI device will be hidden in PCI config space the fast_spi driver could be updated to generate the _CRS and thus mark the SPI_BASE_ADDRESS as reserved.
Change-Id: I150397a7ac5d60719f327f6ac6480a38fe295c32 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/soc/intel/xeon_sp/cpx/soc_acpi.c M src/soc/intel/xeon_sp/skx/soc_acpi.c M src/soc/intel/xeon_sp/spr/soc_acpi.c 3 files changed, 0 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/80795/4