Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32448 )
Change subject: soc/intel/apollolake/bootblock: Clear the GPI IS & IE registers ......................................................................
soc/intel/apollolake/bootblock: Clear the GPI IS & IE registers
Clear the GPI Interrupt Status & Enable registers to prevent any interrupt storms due to GPI.
BUG=b:130593883 BRANCH=octopus TEST=Ensure that the Interrupt status & enable registers are reset during the boot up when the system is brought out of G3, S5 & S3. Ensure that the system boots fine to ChromeOS.
Change-Id: Ia3b9d3bf08472219348e20b53bae470c589039fb Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32448 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/apollolake/bootblock/bootblock.c 1 file changed, 9 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index ac6903a..c791378 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -122,3 +122,12 @@ paging_enable_for_car("pdpt", "pt"); } } + +void bootblock_soc_init(void) +{ + /* + * Clear the GPI interrupt enable & status registers to avoid any + * interrupt storm during the kernel bootup. + */ + gpi_clear_int_cfg(); +}