David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48848 )
Change subject: mb/google/volteer/var/voema: Enable RTD3 for the NVMe device ......................................................................
mb/google/volteer/var/voema: Enable RTD3 for the NVMe device
Enable Runtime D3 for voema that have GPIO power control of the NVMe device attached to PCIe Root Port 9.
BUG=b:169356808 TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: I28ef074225c533e1a97b6ec4a1a5dd1dcc198168 --- M src/mainboard/google/volteer/variants/voema/overridetree.cb 1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/48848/1
diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb index 9efcdb2..8d05c32 100644 --- a/src/mainboard/google/volteer/variants/voema/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -81,6 +81,14 @@ device pnp 0c09.0 on end end end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy.