[coreboot-gerrit] [XS] Change in coreboot[main]: mb/google/brya/bujia: Enable RTD3 for SSD

[Pranava Y N (Code Review)]

Pranava Y N has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86644?usp=email )

Change subject: mb/google/brya/bujia: Enable RTD3 for SSD
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mb/google/brya/bujia: Enable RTD3 for SSD

Add PCIe RTD3 support so NVMe gets placed into D3 state when entering
S0ix. Some SSDs block the CPU from reaching C10 during the S0ix
suspend without the RTD3 configuration.

BUG=b:391612392
TEST=Run suspend_stress_test on Bujia and verify that the device
suspends to S0ix.

Change-Id: Idee14e7d4df0a9cf8b06b33a52016c1b9228e459
Signed-off-by: Pranava Y N 
---
M src/mainboard/google/brya/variants/bujia/overridetree.cb
1 file changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/86644/1

diff --git a/src/mainboard/google/brya/variants/bujia/overridetree.cb b/src/mainboard/google/brya/variants/bujia/overridetree.cb
index 6db60ac..370c052 100644
--- a/src/mainboard/google/brya/variants/bujia/overridetree.cb
+++ b/src/mainboard/google/brya/variants/bujia/overridetree.cb
@@ -119,6 +119,13 @@
    			.clk_src = 0,
    			.flags = PCIE_RP_LTR | PCIE_RP_AER,
    		}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "0"
+				device generic 0 on end
+			end
    	end #NVME
    	device ref tbt_pcie_rp0 off end
    	device ref tbt_pcie_rp1 off end