[coreboot-gerrit] Change in coreboot[master]: sb/intel/bd82x6x: Use <device/azalia_device.h> registers

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44127 )

Change subject: sb/intel/bd82x6x: Use <device/azalia_device.h> registers
......................................................................

sb/intel/bd82x6x: Use <device/azalia_device.h> registers

Change-Id: I1e30dd7b300d7975e7a89fbe1e66aaf7affd1702
Signed-off-by: Elyes HAOUAS 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44127
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
---
M src/southbridge/intel/bd82x6x/azalia.c
1 file changed, 12 insertions(+), 16 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index 4f5d8ca..3d4f7ca 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -12,10 +12,6 @@
 #include "chip.h"
 #include "pch.h"

-#define HDA_ICII_REG 0x68
-#define HDA_ICII_BUSY (1 << 0)
-#define HDA_ICII_VALID (1 << 1)
-
 typedef struct southbridge_intel_bd82x6x_config config_t;

static int set_bits(void *port, u32 mask, u32 val)
@@ -52,15 +48,15 @@
    u8 reg8;

/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
-	if (set_bits(base + 0x08, 1, 1) == -1)
+	if (set_bits(base + HDA_GCTL_REG, 1, 1) == -1)
    	goto no_codec;

/* Write back the value once reset bit is set. */
-	write16(base + 0x0,
-		read16(base + 0x0));
+	write16(base + HDA_GCAP_REG,
+		read16(base + HDA_GCAP_REG));

/* Read in Codec location (BAR + 0xe)[2..0]*/
-	reg8 = read8(base + 0xe);
+	reg8 = read8(base + HDA_STATESTS_REG);
    reg8 &= 0x0f;
    if (!reg8)
    	goto no_codec;
@@ -70,7 +66,7 @@
 no_codec:
    /* Codec Not found */
    /* Put HDA back in reset (BAR + 0x8) [0] */
-	set_bits(base + 0x08, 1, 0);
+	set_bits(base + HDA_GCTL_REG, 1, 0);
    printk(BIOS_DEBUG, "Azalia: No codec!\n");
    return 0;
 }
@@ -159,14 +155,14 @@
    }

reg32 = (addr << 28) | 0x000f0000;
-	write32(base + 0x60, reg32);
+	write32(base + HDA_IC_REG, reg32);

if (wait_for_valid(base) == -1) {
    	printk(BIOS_DEBUG, "  codec not valid.\n");
    	return;
    }

-	reg32 = read32(base + 0x64);
+	reg32 = read32(base + HDA_IR_REG);

/* 2 */
    printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
@@ -183,7 +179,7 @@
    	if (wait_for_ready(base) == -1)
    		return;

-		write32(base + 0x60, verb[i]);
+		write32(base + HDA_IC_REG, verb[i]);

if (wait_for_valid(base) == -1)
    		return;
@@ -203,7 +199,7 @@
    	if (wait_for_ready(base) == -1)
    		return;

-		write32(base + 0x60, pc_beep_verbs[i]);
+		write32(base + HDA_IC_REG, pc_beep_verbs[i]);

if (wait_for_valid(base) == -1)
    		return;
@@ -268,9 +264,9 @@
    /* Codec Initialization Programming Sequence */

/* Take controller out of reset */
-	reg32 = read32(base + 0x08);
-	reg32 |= (1 << 0);
-	write32(base + 0x08, reg32);
+	reg32 = read32(base + HDA_GCTL_REG);
+	reg32 |= HDA_GCTL_CRST;
+	write32(base + HDA_GCTL_REG, reg32);
    /* Wait 1ms */
    udelay(1000);