Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50562 )
Change subject: soc/amd/cezanne/acpi: Generate MADT LAPIC NMI settings ......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50562/comment/decf4864_9ed6496f PS3, Line 9: I'm not actually sure how to verify that LINT1 is connected to NMI.
Should be able to read the LVT register for LINT1 in the LAPIC, so 0xfee00360 if my math is right. […]
there should also be some coreboot code for that. but if the fsp writes registers, that might be why we're getting the spurious irq warnings. or at least my suspicion is that fsp does some things there that it shouldn't do. haven't fully debugged that issue yet and the last time we tried to work around that on the coreboot side we just ran into more trouble on other platforms. for what coreboot does, have a look at cpu/x86/lapic/lapic.c