Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34699 )
Change subject: northbridge/intel: Rename ram_calc.c to memmap.c ......................................................................
northbridge/intel: Rename ram_calc.c to memmap.c
Use a name consistent with the more recent soc/intel.
Change-Id: Ie69583f28f384eb49517203e1c3867f27e6272de Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34699 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/gm45/Makefile.inc R src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/haswell/Makefile.inc R src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i440bx/Makefile.inc R src/northbridge/intel/i440bx/memmap.c M src/northbridge/intel/i945/Makefile.inc R src/northbridge/intel/i945/memmap.c M src/northbridge/intel/nehalem/Makefile.inc R src/northbridge/intel/nehalem/memmap.c M src/northbridge/intel/pineview/Makefile.inc R src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/sandybridge/Makefile.inc R src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/Makefile.inc R src/northbridge/intel/x4x/memmap.c 16 files changed, 24 insertions(+), 24 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc index b59a7c3..0ab1c94 100644 --- a/src/northbridge/intel/gm45/Makefile.inc +++ b/src/northbridge/intel/gm45/Makefile.inc @@ -25,18 +25,18 @@ romstage-y += thermal.c romstage-y += igd.c romstage-y += pm.c -romstage-y += ram_calc.c +romstage-y += memmap.c romstage-y += iommu.c romstage-y += romstage.c
ramstage-y += acpi.c
-ramstage-y += ram_calc.c +ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += gma.c
smm-y += ../../../cpu/x86/lapic/apic_timer.c
-postcar-y += ram_calc.c +postcar-y += memmap.c
endif diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/memmap.c similarity index 100% rename from src/northbridge/intel/gm45/ram_calc.c rename to src/northbridge/intel/gm45/memmap.c diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index ca1c04f..b986336 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -17,14 +17,14 @@
bootblock-y += bootblock.c
-ramstage-y += ram_calc.c +ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += gma.c
ramstage-y += acpi.c ramstage-y += minihd.c
-romstage-y += ram_calc.c +romstage-y += memmap.c romstage-y += raminit.c romstage-y += early_init.c romstage-y += report_platform.c @@ -37,6 +37,6 @@ mrc.bin-position := 0xfffa0000 mrc.bin-type := mrc
-postcar-y += ram_calc.c +postcar-y += memmap.c
endif diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/memmap.c similarity index 100% rename from src/northbridge/intel/haswell/ram_calc.c rename to src/northbridge/intel/haswell/memmap.c diff --git a/src/northbridge/intel/i440bx/Makefile.inc b/src/northbridge/intel/i440bx/Makefile.inc index d41f65d..2c503c6 100644 --- a/src/northbridge/intel/i440bx/Makefile.inc +++ b/src/northbridge/intel/i440bx/Makefile.inc @@ -17,12 +17,12 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BX),y)
ramstage-y += northbridge.c -ramstage-y += ram_calc.c +ramstage-y += memmap.c
romstage-y += raminit.c romstage-$(CONFIG_DEBUG_RAM_SETUP) += debug.c -romstage-y += ram_calc.c +romstage-y += memmap.c
-postcar-y += ram_calc.c +postcar-y += memmap.c
endif diff --git a/src/northbridge/intel/i440bx/ram_calc.c b/src/northbridge/intel/i440bx/memmap.c similarity index 100% rename from src/northbridge/intel/i440bx/ram_calc.c rename to src/northbridge/intel/i440bx/memmap.c diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index ffeabdc..47b4c51 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -15,12 +15,12 @@
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I945),y)
-ramstage-y += ram_calc.c +ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += gma.c ramstage-y += acpi.c
-romstage-y += ram_calc.c +romstage-y += memmap.c romstage-y += raminit.c romstage-y += early_init.c romstage-y += errata.c @@ -29,6 +29,6 @@
smm-y += udelay.c
-postcar-y += ram_calc.c +postcar-y += memmap.c
endif diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/memmap.c similarity index 100% rename from src/northbridge/intel/i945/ram_calc.c rename to src/northbridge/intel/i945/memmap.c diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc index c0d46c9..52374ac 100644 --- a/src/northbridge/intel/nehalem/Makefile.inc +++ b/src/northbridge/intel/nehalem/Makefile.inc @@ -15,20 +15,20 @@
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_NEHALEM),y)
-ramstage-y += ram_calc.c +ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += smi.c ramstage-y += gma.c
ramstage-y += acpi.c
-romstage-y += ram_calc.c +romstage-y += memmap.c romstage-y += raminit.c romstage-y += early_init.c romstage-y += ../../../arch/x86/walkcbfs.S
smm-y += finalize.c
-postcar-y += ram_calc.c +postcar-y += memmap.c
endif diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/memmap.c similarity index 100% rename from src/northbridge/intel/nehalem/ram_calc.c rename to src/northbridge/intel/nehalem/memmap.c diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc index 8348771..81ee783 100644 --- a/src/northbridge/intel/pineview/Makefile.inc +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -19,16 +19,16 @@ bootblock-y += ../../../cpu/x86/early_reset.S bootblock-y += bootblock.c
-ramstage-y += ram_calc.c +ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += gma.c ramstage-y += acpi.c
romstage-y += romstage.c -romstage-y += ram_calc.c +romstage-y += memmap.c romstage-y += raminit.c romstage-y += early_init.c
-postcar-y += ram_calc.c +postcar-y += memmap.c
endif diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/memmap.c similarity index 100% rename from src/northbridge/intel/pineview/ram_calc.c rename to src/northbridge/intel/pineview/memmap.c diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 8a0b67b..77d1fdb 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -15,14 +15,14 @@
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE),y)
-ramstage-y += ram_calc.c +ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += pcie.c ramstage-y += gma.c
ramstage-y += acpi.c
-romstage-y += ram_calc.c +romstage-y += memmap.c
ramstage-y += common.c romstage-y += common.c @@ -48,6 +48,6 @@
smm-y += finalize.c
-postcar-y += ram_calc.c +postcar-y += memmap.c
endif diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/memmap.c similarity index 100% rename from src/northbridge/intel/sandybridge/ram_calc.c rename to src/northbridge/intel/sandybridge/memmap.c diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc index 3118b09..b7fd2fe 100644 --- a/src/northbridge/intel/x4x/Makefile.inc +++ b/src/northbridge/intel/x4x/Makefile.inc @@ -19,16 +19,16 @@ romstage-y += early_init.c romstage-y += raminit.c romstage-y += raminit_ddr23.c -romstage-y += ram_calc.c +romstage-y += memmap.c romstage-y += rcven.c romstage-y += raminit_tables.c romstage-y += dq_dqs.c
ramstage-y += acpi.c -ramstage-y += ram_calc.c +ramstage-y += memmap.c ramstage-y += gma.c ramstage-y += northbridge.c
-postcar-y += ram_calc.c +postcar-y += memmap.c
endif diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/memmap.c similarity index 100% rename from src/northbridge/intel/x4x/ram_calc.c rename to src/northbridge/intel/x4x/memmap.c