[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block/cpu: Enable ROM caching in ramstage

[Subrata Banik (Code Review)]

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Angel Pons, Nick Vaccaro.
Subrata Banik has uploaded a new patch set (#2) to the change originally created by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/62838 )

Change subject: soc/intel/common/block/cpu: Enable ROM caching in ramstage
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soc/intel/common/block/cpu: Enable ROM caching in ramstage

Cache the BIOS region and extended BIOS region if the boot device is
memory mapped, which is mostly the case with Intel SoC platform.
Having the ROM region cached helped to improve the pre-boot time.

TEST=Able to boot redrix to Chrome OS without seeing any sluggishness.
Additionally verified on EHL board (from siemens), shows significant
savings in payload loading time as below:

Here is the timestamp snippet showing the payload load time as a
comparison between current upstream and the patched version:

upstream:
  90:starting to load payload                    1,072,459 (1,802)
 958:calling FspNotify(ReadyToBoot)              12,818,079 (11,745,619)

with this patch:
  90:starting to load payload                    1,072,663 (2,627)
 958:calling FspNotify(ReadyToBoot)              5,299,535 (4,226,871)

Signed-off-by: Subrata Banik 
Change-Id: I02b80eefbb3b19331698a205251a0c4d17be534c
---
M src/soc/intel/common/block/cpu/mp_init.c
1 file changed, 9 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/62838/2