15 Jul
2020
15 Jul
'20
12:41 p.m.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35406 )
Change subject: soc/intel/common/block: Stitch CSE blobs into FW_MAIN_X partitions ......................................................................
Patch Set 62:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35406/62/src/soc/intel/common/block... File src/soc/intel/common/block/cse/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/35406/62/src/soc/intel/common/block... PS62, Line 9: INTERMEDIATE+=add_intel_me_rw
Why?
Looks like following the example at src/southbridge/intel/common/firmware/Makefile.inc for add_intel_firmware
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I1d2908e9e16858c5f333e1b10b19d18b7ca27765
Gerrit-Change-Number: 35406
Gerrit-PatchSet: 62
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