Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41075 )
Change subject: soc/amd/picasso: Enable eSPI capability for Picasso ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41075/11/src/soc/amd/picasso/southb... File src/soc/amd/picasso/southbridge.c:
https://review.coreboot.org/c/coreboot/+/41075/11/src/soc/amd/picasso/southb... PS11, Line 210: PICASSO_LPC_IOMUX
I do however get more post codes on the LPC-attached port 0x80 LED display thing
I think that is expected because lpc_enable_port80() gets called when SOC_AMD_COMMON_BLOCK_USE_ESPI is not selected.
Not sure if missing LPC pin mux setup is the issue here or if the decode ranges just end up on the wrong bus. The name of PICASSO_LPC_IOMUX suggests that it should do something with the LPC/eMMC muxing; haven't further looked into the issue though.
There was no common code in soc/amd that was using PICASSO_LPC_IOMUX to control eMMC initialization. I think all of it lives under mainboard/amd/mandolin.