[coreboot-gerrit] Change in coreboot[master]: sb/intel/lynxpoint: Enable/disable AER via Kconfig

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46133 )

Change subject: sb/intel/lynxpoint: Enable/disable AER via Kconfig
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sb/intel/lynxpoint: Enable/disable AER via Kconfig

Semi-recent changes to the Linux kernel now enable AER for many
devices for which it was previously disabled. This, coupled with
the SB enabling AER for all PCIe devices, has resulted in a large
amount of AER timeout errors in the kernel log for devices which
do not support AER. To mitigate this, guard AER enablement via
Kconfig, select it by default (as to maintain current default
behavior), and allow boards which need to disable it to do so.

This implementation is identical to/copied from soc/intel/broadwell.

Test: build/boot google/beltino variants with AER disabled, verify
dmesg log free of AER errors.

Change-Id: Ia03ef0d111335892c65122954c1248191ded7cb8
Signed-off-by: Matt DeVillier 
---
M src/southbridge/intel/lynxpoint/Kconfig
M src/southbridge/intel/lynxpoint/pcie.c
2 files changed, 11 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/46133/1

diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index c104cbb..43f8bce 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -58,4 +58,8 @@
      If you set this option to y, the USB ports will be routed
      to the XHCI controller during the finalize SMM callback.

+config PCIEXP_AER
+	bool
+	default y
+
 endif
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 35ce5c47..42e002b 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -670,8 +670,13 @@
    /* Set EOI forwarding disable. */
    pci_or_config32(dev, 0xd4, 1 << 1);

-	/* Set something involving advanced error reporting. */
-	pci_update_config32(dev, 0x100, ~((1 << 20) - 1), 0x10001);
+	/* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */
+	if (CONFIG(PCIEXP_AER))
+		pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff,
+			(1 << 29) | 0x10001);
+	else
+		pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff,
+			(1 << 29));

if (is_lp)
    	pci_or_config32(dev, 0x100, 1 << 29);