Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30686
Change subject: [WIP]soc/fsp1.1: Implement postcar stage ......................................................................
[WIP]soc/fsp1.1: Implement postcar stage
TODO cleanup, test
Change-Id: I2330993842aae9c1365230f0c6bd8a2449dc73a5 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/drivers/intel/fsp1_1/Kconfig M src/drivers/intel/fsp1_1/Makefile.inc M src/drivers/intel/fsp1_1/after_raminit.S M src/drivers/intel/fsp1_1/cache_as_ram.inc M src/drivers/intel/fsp1_1/romstage.c M src/soc/intel/braswell/Makefile.inc M src/soc/intel/skylake/romstage/car_stage.S 7 files changed, 86 insertions(+), 159 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/30686/1
diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 69fa8df..53a993c 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -18,6 +18,8 @@ bool select UEFI_2_4_BINDING select INTEL_GMA_ADD_VBT if RUN_FSP_GOP + select POSTCAR_STAGE + select POSTCAR_CONSOLE help Does the code require the Intel Firmware Support Package?
diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 953d1e4..62dc663 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -28,7 +28,6 @@ romstage-y += hob.c romstage-y += raminit.c romstage-y += romstage.c -romstage-y += stack.c romstage-y += stage_cache.c romstage-$(CONFIG_MMA) += mma_core.c
@@ -45,6 +44,9 @@
cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_1/cache_as_ram.inc
+postcar-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += after_raminit.S +postcar-y += stage_cache.c + # Add the FSP binary to the cbfs image ifeq ($(CONFIG_HAVE_FSP_BIN),y) cbfs-files-y += fsp.bin diff --git a/src/drivers/intel/fsp1_1/after_raminit.S b/src/drivers/intel/fsp1_1/after_raminit.S index cdc8e93..05c4425 100644 --- a/src/drivers/intel/fsp1_1/after_raminit.S +++ b/src/drivers/intel/fsp1_1/after_raminit.S @@ -20,151 +20,10 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h>
-/* - * This is the common entry point after DRAM has been initialized. - */ - /* - * eax: New stack address - */ - - /* Switch to the stack in RAM */ - movl %eax, %esp - -#if IS_ENABLED(CONFIG_SKIP_FSP_CAR) - - /* chipset_teardown_car() is expected to disable cache-as-ram. */ - call chipset_teardown_car - -#else -.extern fih_car +.text +.global chipset_teardown_car +chipset_teardown_car:
post_code(POST_FSP_TEMP_RAM_EXIT) - - /* Calculate TempRamExit entry into FSP */ - movl fih_car, %ebp - mov 0x40(%ebp), %eax - add 0x1c(%ebp), %eax - - /* Build the call frame */ - pushl $0 - - /* Call TempRamExit */ - call *%eax - add $4, %esp - cmp $0, %eax - jz 1f - /* - * Failures for post code BC - failed in TempRamExit - * - * 0x00 - FSP_SUCCESS: Temp RAM Exit completed successfully. - * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid. - * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met. - * 0x07 - FSP_DEVICE_ERROR: Temp RAM Exit failed. - */ - movb $0xBC, %ah - jmp .Lhlt -1: -#endif - /* Display the MTRRs */ - call display_mtrrs - - /* - * The stack contents are initialized in src/soc/intel/common/stack.c - * to be the following: - * - * * - * * - * * - * +36: MTRR mask 1 63:32 - * +32: MTRR mask 1 31:0 - * +28: MTRR base 1 63:32 - * +24: MTRR base 1 31:0 - * +20: MTRR mask 0 63:32 - * +16: MTRR mask 0 31:0 - * +12: MTRR base 0 63:32 - * +8: MTRR base 0 31:0 - * +4: Number of MTRRs to setup (described above) - * +0: Number of variable MTRRs to clear - */ - -#if IS_ENABLED(CONFIG_SOC_SETS_MSRS) - push %esp - call soc_set_mtrrs - - /* eax: new top_of_stack with setup_stack_and_mtrrs data removed */ - movl %eax, %esp -#else - /* Clear all of the variable MTRRs. */ - popl %ebx - movl $MTRR_PHYS_BASE(0), %ecx - clr %eax - clr %edx - -1: - testl %ebx, %ebx - jz 1f - wrmsr /* Write MTRR base. */ - inc %ecx - wrmsr /* Write MTRR mask. */ - inc %ecx - dec %ebx - jmp 1b - -1: - /* Get number of MTRRs. */ - popl %ebx - movl $MTRR_PHYS_BASE(0), %ecx -2: - testl %ebx, %ebx - jz 2f - - /* Low 32 bits of MTRR base. */ - popl %eax - /* Upper 32 bits of MTRR base. */ - popl %edx - /* Write MTRR base. */ - wrmsr - inc %ecx - /* Low 32 bits of MTRR mask. */ - popl %eax - /* Upper 32 bits of MTRR mask. */ - popl %edx - /* Write MTRR mask. */ - wrmsr - inc %ecx - - dec %ebx - jmp 2b -2: -#endif /* CONFIG_SOC_SETS_MSRS */ - - post_code(0x39) - - /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax - movl %eax, %cr0 - - post_code(0x3a) - -#if IS_ENABLED(CONFIG_SOC_SETS_MSRS) - call soc_enable_mtrrs -#else - /* Enable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - orl $MTRR_DEF_TYPE_EN, %eax - wrmsr -#endif /* CONFIG_SOC_SETS_MSRS */ - - post_code(0x3b) - - /* Invalidate the cache again. */ - invd - - post_code(0x3c) - -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - call after_cache_as_ram + pop %ebx + jmp *%ebx diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index 934ae67..2a4e47c 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -140,11 +140,6 @@ /* Call cache_as_ram_main(struct cache_as_ram_params *) */ call cache_as_ram_main
-/* One will never return from cache_as_ram_main() in verstage so there's - * no such thing as after RAM init. */ -#if !ENV_VERSTAGE -#include "after_raminit.S" -#endif
movb $0x69, %ah jmp .Lhlt diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index c1bcd84..d362b44 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -30,6 +30,7 @@ #include <ec/google/chromeec/ec_commands.h> #include <elog.h> #include <fsp/romstage.h> +#include <fsp/memmap.h> #include <mrc_cache.h> #include <program_loading.h> #include <romstage_handoff.h> @@ -39,9 +40,77 @@ #include <timestamp.h> #include <vendorcode/google/chromeos/chromeos.h>
+#define ROMSTAGE_RAM_STACK_SIZE 0x5000 + +/* platform_enter_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use, + * and continues execution in postcar stage. */ +static void platform_enter_postcar(void) +{ + struct postcar_frame pcf; + size_t alignment; + uint32_t aligned_ram; + + if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + die("Unable to initialize postcar frame.\n"); + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* + * +-------------------------+ Top of RAM (aligned) + * | System Management Mode | + * | code and data | Length: CONFIG_TSEG_SIZE + * | (TSEG) | + * +-------------------------+ SMM base (aligned) + * | | + * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE + * | | + * +-------------------------+ top_of_ram (aligned) + * | | + * | CBMEM Root | + * | | + * +-------------------------+ + * | | + * | FSP Reserved Memory | + * | | + * +-------------------------+ + * | | + * | Various CBMEM Entries | + * | | + * +-------------------------+ top_of_stack (8 byte aligned) + * | | + * | stack (CBMEM Entry) | + * | | + * +-------------------------+ + */ + + alignment = mmap_region_granularity(); + aligned_ram = ALIGN_DOWN(romstage_ram_stack_bottom(), alignment); + postcar_frame_add_mtrr(&pcf, aligned_ram, aligned_ram + alignment, MTRR_TYPE_WRBACK); + +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) + uintptr_t smm_base; + size_t smm_size; + + /* + * Cache the TSEG region at the top of ram. This region is not + * restricted to SMM mode until SMM has been relocated. By setting + * the region to cacheable it provides faster access when relocating + * the SMM handler as well as using the TSEG region for other purposes. + */ + smm_region(&smm_base, &smm_size); + postcar_frame_add_mtrr(&pcf, smm_base, alignment, MTRR_TYPE_WRBACK); +#endif + + run_postcar_phase(&pcf); +} + asmlinkage void *romstage_main(FSP_INFO_HEADER *fih) { - void *top_of_stack; struct pei_data pei_data; struct romstage_params params = { .pei_data = &pei_data, @@ -78,11 +147,9 @@ soc_after_ram_init(¶ms); post_code(0x38);
- top_of_stack = setup_stack_and_mtrrs(); + platform_enter_postcar();
- printk(BIOS_DEBUG, "Calling FspTempRamExit API\n"); - timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_START); - return top_of_stack; + return NULL; }
void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih) diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index fabbc2b..3296331 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -16,6 +16,9 @@ romstage-y += pmutil.c romstage-y += tsc_freq.c
+postcar-y += memmap.c +postcar-y += iosf.c + ramstage-y += acpi.c ramstage-y += chip.c ramstage-y += cpu.c diff --git a/src/soc/intel/skylake/romstage/car_stage.S b/src/soc/intel/skylake/romstage/car_stage.S index 9482456..1c5857b 100644 --- a/src/soc/intel/skylake/romstage/car_stage.S +++ b/src/soc/intel/skylake/romstage/car_stage.S @@ -20,9 +20,8 @@ .global car_stage_entry car_stage_entry: call romstage_c_entry - #include "src/drivers/intel/fsp1_1/after_raminit.S"
- + /* we don't return here */ movb $0x69, %ah jmp .Lhlt