[coreboot-gerrit] Change in coreboot[master]: [Test Only]mainboard/intel/glkrvp: Configure Prmrr and SGX

[Pratikkumar V Prajapati (Code Review)]

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21278

Change subject: [Test Only]mainboard/intel/glkrvp: Configure Prmrr and SGX
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[Test Only]mainboard/intel/glkrvp: Configure Prmrr and SGX

DO NOT MERGE.
This patch is for test only.

Change-Id: Ifa39df4a1da84bae49551a9626257bda0729752b
Signed-off-by: Pratik Prajapati 
---
M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
1 file changed, 8 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/21278/1

diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
index e8eb3f3..59fe917 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
@@ -86,6 +86,14 @@
    # Minimum SLP S3 assertion width 28ms.
    register "slp_s3_assertion_width_usecs" = "28000"

+	register "sgx_enable" = "1"
+
+	# PRMRR size
+	# 0x02000000 - 32MiB
+	# 0x04000000 - 64MiB
+	# 0x08000000 - 128MiB
+	register "PrmrrSize" = "0x08000000"
+
    device domain 0 on
    	device pci 00.0 on  end	# - Host Bridge
    	device pci 00.1 on  end	# - DPTF