[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp/cpx: Enable SATA ports

[Maxim Polyakov (Code Review)]

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39918 )

Change subject: soc/intel/xeon_sp/cpx: Enable SATA ports
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Patch Set 2: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/39918/2/src/soc/intel/xeon_sp/cpx/K... 
File src/soc/intel/xeon_sp/cpx/Kconfig:

https://review.coreboot.org/c/coreboot/+/39918/2/src/soc/intel/xeon_sp/cpx/K... 
PS2, Line 20: SOC_INTEL_COMMON_BLOCK_SATA
It seems to me that the mask in the common code https://github.com/coreboot/coreboot/blob/7eeaeeecc590d22a8f51175ba07cf2cfad...
isn't correct, because in the C620 we have 8 ports, as in the 200/300 series chipset.
In this case, we can only change the state of the first four ports.
What do you think about this? Maybe this mask is valid for mobile versions of processors.