[coreboot-gerrit] Change in coreboot[master]: [WIP] soc/amd/picasso/mca: fix CTL_MASK access

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson.
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52583 )

Change subject: [WIP] soc/amd/picasso/mca: fix CTL_MASK access
......................................................................

[WIP] soc/amd/picasso/mca: fix CTL_MASK access

MC0_CTL_MASK is no longer available in fam 17h and newer and will result
in a general protection fault when accessed. This register was moved to
the MCAX banks, so use that.

TODO: add proper defines and don't use a magic MSR register index

BUG=b:186038401

Signed-off-by: Felix Held 
Change-Id: Ibb042635d917dfcb2121849e2913aa62eca09dd0
---
M src/soc/amd/picasso/mca.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/52583/1

diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c
index 16471b9..48a0a1f 100644
--- a/src/soc/amd/picasso/mca.c
+++ b/src/soc/amd/picasso/mca.c
@@ -122,7 +122,7 @@
    if (!ctx)
    	goto failed;
    ctx = cper_new_ia32x64_context_msr(status, x86_sec,
-					MC0_CTL_MASK + mci->bank, 1);
+					0xc0010400 + mci->bank, 1);
    if (!ctx)
    	goto failed;

@@ -176,7 +176,7 @@
    			mci.ctl = rdmsr(IA32_MC0_CTL + (i * 4));
    			printk(BIOS_WARNING, "   MC%d_CTL =      %08x_%08x\n",
    					i, mci.ctl.hi, mci.ctl.lo);
-				mci.cmask = rdmsr(MC0_CTL_MASK + i);
+				mci.cmask = rdmsr(0xc0010400 + i);
    			printk(BIOS_WARNING, "   MC%d_CTL_MASK = %08x_%08x\n",
    					i, mci.cmask.hi, mci.cmask.lo);