Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56359 )
Change subject: soc/amd: Rename fill_chipset_state as pm_cache_chipset_state ......................................................................
soc/amd: Rename fill_chipset_state as pm_cache_chipset_state
Chipset power state is cached before any FSP call and later is added to CBMEM. Rename the function to match its purpose so that the fill operation can be added later to log any modern standby wake source.
BUG=None TEST=Build and boot to OS in Guybrush.
Change-Id: I67b302227d79bacc5300f31b9428c66cc530c6bc Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/soc/amd/cezanne/romstage.c M src/soc/amd/common/block/include/amdblocks/pmlib.h M src/soc/amd/common/block/pm/chipset_state.c M src/soc/amd/picasso/romstage.c 4 files changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/56359/1
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index 9e863c3..37c2bcd 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -21,7 +21,7 @@ post_code(0x41);
/* Snapshot chipset state prior to any FSP call */ - fill_chipset_state(); + pm_cache_chipset_state();
fsp_memory_init(acpi_is_wakeup_s3());
diff --git a/src/soc/amd/common/block/include/amdblocks/pmlib.h b/src/soc/amd/common/block/include/amdblocks/pmlib.h index d9b80a2..fae48cb 100644 --- a/src/soc/amd/common/block/include/amdblocks/pmlib.h +++ b/src/soc/amd/common/block/include/amdblocks/pmlib.h @@ -18,6 +18,6 @@ void pm_set_power_failure_state(void);
/* stash ACPI PM/GPE and GPIO wake state before FSP-M call */ -void fill_chipset_state(void); +void pm_cache_chipset_state(void);
#endif /* SOC_AMD_COMMON_BLOCK_PMLIB_H */ diff --git a/src/soc/amd/common/block/pm/chipset_state.c b/src/soc/amd/common/block/pm/chipset_state.c index 3a4a0ba..abe64d7 100644 --- a/src/soc/amd/common/block/pm/chipset_state.c +++ b/src/soc/amd/common/block/pm/chipset_state.c @@ -8,7 +8,7 @@
static struct chipset_power_state chipset_state;
-void fill_chipset_state(void) +void pm_cache_chipset_state(void) { acpi_fill_pm_gpe_state(&chipset_state.gpe_state); gpio_fill_wake_state(&chipset_state.gpio_state); diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 1972410..e702649 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -22,7 +22,7 @@ post_code(0x42);
/* Snapshot chipset state prior to any FSP call. */ - fill_chipset_state(); + pm_cache_chipset_state();
post_code(0x43); fsp_memory_init(acpi_is_wakeup_s3());