Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38490 )
Change subject: soc/mediatek/mt8183: improve the DRAMC runtime config flow ......................................................................
Patch Set 3:
(4 comments)
https://review.coreboot.org/c/coreboot/+/38490/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38490/3//COMMIT_MSG@11 PS3, Line 11: BUG=b:none BUG=none
https://review.coreboot.org/c/coreboot/+/38490/1/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/38490/1/src/soc/mediatek/mt8183/dra... PS1, Line 290: (0x7 << 28) | (0x7 << 24), (0x1 << 28) | (0x0 << 24));
Done
I meant
clrsetbits32(&ch[chn].phy.b[b].dq[9], (0x7 << 28) | (0x7 << 24), (0x1 << 28) | (0x0 << 24));
I know most of the code in this file doesn't align like this, but we should do it while we're at it.
https://review.coreboot.org/c/coreboot/+/38490/1/src/soc/mediatek/mt8183/dra... PS1, Line 326: (0x7 << 22) | (0x3 << 14) | (0x1 << 19) | (0x1 << 21));
Done
I meant
clrbits32(&ch[chn].ao.stbcal, (0x7 << 22) | (0x3 << 14) | (0x1 << 19) | (0x1 << 21));
https://review.coreboot.org/c/coreboot/+/38490/1/src/soc/mediatek/mt8183/dra... PS1, Line 381: setbits32(&ch[chn].ao.dummy_rd, 0x1 << 25 | 0x1 << 20);
is a bug fix
Could you move all the bug fixes to a separate CL? It's hard to tell bug fixes from improvement.