Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38608 )
Change subject: WIP: Move SA _CRS to runtime SSDT generator ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38608/1/src/soc/intel/common/block/... File src/soc/intel/common/block/systemagent/systemagent.c:
https://review.coreboot.org/c/coreboot/+/38608/1/src/soc/intel/common/block/... PS1, Line 344: /* DMI BAR */ : acpigen_write_mem32fixed(1, DMI_BASE_ADDRESS, DMI_BASE_SIZE); : : /* EP BAR */ : acpigen_write_mem32fixed(1, EP_BASE_ADDRESS, EP_BASE_SIZE)
i don't see this in APL/GLK EDS
Ack. Yes, like I said above I think we don't even need to add any of this information here. We can reuse the fixed mmio resources already added by SoC. I will fix it in the next revision of the patch.
https://review.coreboot.org/c/coreboot/+/38608/1/src/soc/intel/common/block/... PS1, Line 353: /* VTD */
we have to use VTD Kconfig
Same as above.