[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port()

[Richard Spiegel (Code Review)]

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28342

Change subject: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port()
......................................................................

soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port()

Function pci_ehci_dbg_set_port() used NDA register DEBUGPORT_MISC_CONTROL,
which was deprecated in favor of a public PCI register (though only the
bits to enable debug port became public) 0x90. Therefor code needs to be
updated.

BUG=b:69231009
TEST=Build and boot grunt.

Change-Id: I5938ada96999774bd998998d47686427ec34d4d1
Signed-off-by: Richard Spiegel 
---
M src/soc/amd/stoneyridge/include/soc/southbridge.h
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/28342/1

diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 5f1faea..acbd6ec 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -308,7 +308,7 @@
 #define EHCI_HUB_CONFIG4		0x90
 #define   DEBUG_PORT_SELECT_SHIFT	  16
 #define   DEBUG_PORT_ENABLE		  BIT(18)
-#define   DEBUG_PORT_MASK		( BIT(16) | BIT(17) | (BIT(18) )
+#define   DEBUG_PORT_MASK		((BIT(16) | BIT(17) | (BIT(18)))

#define WIDEIO_RANGE_ERROR		-1
 #define TOTAL_WIDEIO_PORTS		3