[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Speed up postcar loading using intermediate cac...

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34791 )

Change subject: soc/intel/cannonlake: Speed up postcar loading using intermediate caching
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Patch Set 10:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34791/9/src/soc/intel/cannonlake/ro... 
File src/soc/intel/cannonlake/romstage/romstage.c:

https://review.coreboot.org/c/coreboot/+/34791/9/src/soc/intel/cannonlake/ro... 
PS9, Line 167: 	/* Cache the ROM as WP just below 4GiB. */
> run_ramstage() has this: […]

yes, ramstage execution will help for sure. Today postcar MTRR frame has only 2 MTRR range (atleast on IA side i can tell, latest platform)

1.ROM mapped 
2. DRAM top 16MB

both these ranges doesn't cover your TSEG range which will be higher address space than Bootloader TOLUM memory, hence you can enable caching for that range as well if you wish