Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52905 )
Change subject: [UNTESTED] soc/amd/cezanne: add GNB IOAPIC support ......................................................................
[UNTESTED] soc/amd/cezanne: add GNB IOAPIC support
To configure and enable the IOAPIC in the graphics and northbridge (GNB) container, FSP needs to write an undocumented register, so pass the GNB IOAPIC MMIO base address to make it show up at that address.
BUG=b:187083211
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I1e127ce500d052783f0a6e13fb2ad16a8e408b0e --- M src/soc/amd/cezanne/fsp_m_params.c M src/soc/amd/cezanne/include/soc/iomap.h M src/soc/amd/cezanne/root_complex.c 3 files changed, 27 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/52905/1
diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index 8da38ff..4aff7e0 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/apob_cache.h> +#include <amdblocks/ioapic.h> #include <amdblocks/memmap.h> #include <assert.h> #include <console/uart.h> @@ -50,6 +51,13 @@ fill_ddi_descriptors(mcfg, fsp_ddi, num_ddi); }
+static void fsp_assign_ioapic_upds(FSP_M_CONFIG *mcfg) +{ + mcfg->gnb_ioapic_base = GNB_IO_APIC_ADDR; + mcfg->gnb_ioapic_id = GNB_IOAPIC_ID; + mcfg->fch_ioapic_id = FCH_IOAPIC_ID; +} + void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { FSP_M_CONFIG *mcfg = &mupd->FspmConfig; @@ -129,4 +137,5 @@ config->telemetry_vddcrsocoffset;
fsp_fill_pcie_ddi_descriptors(mcfg); + fsp_assign_ioapic_upds(mcfg); } diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index 83bb817..486e3cf 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -11,6 +11,8 @@ #if ENV_X86
/* MMIO Ranges */ +/* IO_APIC_ADDR defined in arch/x86 0xfec00000 */ +#define GNB_IO_APIC_ADDR 0xfec01000 #define SPI_BASE_ADDRESS 0xfec10000
#if CONFIG(HPET_ADDRESS_OVERRIDE) diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index ba84681..5d021ba 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/acpi.h> +#include <amdblocks/ioapic.h> #include <amdblocks/memmap.h> +#include <arch/ioapic.h> #include <cbmem.h> #include <console/console.h> #include <cpu/amd/msr.h> @@ -9,6 +11,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <fsp/util.h> +#include <soc/iomap.h> #include <stdint.h>
/* @@ -70,6 +73,7 @@ unsigned int idx = 0; const struct hob_header *hob = fsp_get_hob_list(); const struct hob_resource *res; + struct resource *gnb_apic;
uintptr_t early_reserved_dram_start, early_reserved_dram_end; const struct memmap_early_dram *e = memmap_get_early_dram_usage(); @@ -129,6 +133,17 @@ printk(BIOS_ERR, "Error: failed to set resources for type %d\n", res->type); } + + /* GNB IOAPIC resource */ + gnb_apic = new_resource(dev, GNB_IO_APIC_ADDR); + gnb_apic->base = GNB_IO_APIC_ADDR; + gnb_apic->size = 0x00001000; + gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void root_complex_init(struct device *dev) +{ + setup_ioapic((u8 *)GNB_IO_APIC_ADDR, GNB_IOAPIC_ID); }
static void root_complex_fill_ssdt(const struct device *device) @@ -145,6 +160,7 @@ .read_resources = read_resources, .set_resources = noop_set_resources, .enable_resources = pci_dev_enable_resources, + .init = root_complex_init, .acpi_name = gnb_acpi_name, .acpi_fill_ssdt = root_complex_fill_ssdt, };