[coreboot-gerrit] Change in coreboot[master]: vc/amd/agesa/[...]/Proc/Mem: Fix uninitialized scalar variable

[Name of user not set (Code Review)]

[e-mail] has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38495 )

Change subject: vc/amd/agesa/[...]/Proc/Mem: Fix uninitialized scalar variable
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vc/amd/agesa/[...]/Proc/Mem: Fix uninitialized scalar variable

FinalRxEnCycle[ByteLane] does not get set in mtthrcSeedTrain.c if
(((UINT16) FinalRxEnCycle[ByteLane] >= NBPtr->MinRxEnSeedGross) && \
 ((UINT16) FinalRxEnCycle[ByteLane] <= NBPtr->MaxRxEnSeedTotal))
evaluates FALSE. According to Coverity, this could result in cases where
RxEnDlyTargetValue[ByteLane] = FinalRxEnCycle[ByteLane] is used with an
uninitialized value. Move the FinalRxEnCycle[ByteLane] initial assignment
up a line so it gets initialized regardless. Tested on Lenovo G505s.

Change-Id: Id1d3580c8915ba31e87059851fec2ae4b8b0e1da
Signed-off-by: Joe Moore 
Found-by: Coverity CID 1370599
---
M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c
M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c
2 files changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/38495/1

diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c
index 991667b..d21c246 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c
@@ -504,8 +504,8 @@
       for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) {
         if (RxEnDlyTargetFound[ByteLane] == FALSE) {
           MemClkCycle = (UINT8) (FailTestRxEnDly[ByteLane] >> 5);
+          FinalRxEnCycle[ByteLane] = PassTestRxEnDly[ByteLane] - 0x10;
           if (RxEnMemClkTested[ByteLane][MemClkCycle] ? RxEnMemClkSt[ByteLane][MemClkCycle] == TRUE : (TechPtr->ByteLaneError[ByteLane] && DlyWrittenToReg[ByteLane])) {
-            FinalRxEnCycle[ByteLane] = PassTestRxEnDly[ByteLane] - 0x10;
             if (((UINT16) FinalRxEnCycle[ByteLane] >= NBPtr->MinRxEnSeedGross) && ((UINT16) FinalRxEnCycle[ByteLane] <= NBPtr->MaxRxEnSeedTotal)) {
               // Since FailTestRxEnDly, we can set FinalRxEnCycle
               MemTRdPosRxEnSeedSetDly3 (TechPtr, (UINT16) FinalRxEnCycle[ByteLane], ByteLane);
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c
index 1446f3e..7ea7c56 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c
@@ -505,8 +505,8 @@
       for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) {
         if (RxEnDlyTargetFound[ByteLane] == FALSE) {
           MemClkCycle = (UINT8) (FailTestRxEnDly[ByteLane] >> 5);
+          FinalRxEnCycle[ByteLane] = PassTestRxEnDly[ByteLane] - 0x10;
           if (RxEnMemClkTested[ByteLane][MemClkCycle] ? RxEnMemClkSt[ByteLane][MemClkCycle] == TRUE : (TechPtr->ByteLaneError[ByteLane] && DlyWrittenToReg[ByteLane])) {
-            FinalRxEnCycle[ByteLane] = PassTestRxEnDly[ByteLane] - 0x10;
             if (((UINT16) FinalRxEnCycle[ByteLane] >= NBPtr->MinRxEnSeedGross) && ((UINT16) FinalRxEnCycle[ByteLane] <= NBPtr->MaxRxEnSeedTotal)) {
               // Since FailTestRxEnDly, we can set FinalRxEnCycle
               MemTRdPosRxEnSeedSetDly3 (TechPtr, (UINT16) FinalRxEnCycle[ByteLane], ByteLane);