build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39847 )
Change subject: soc/intel/tigerlake: Support to initialize Memory ......................................................................
Patch Set 13:
(25 comments)
https://review.coreboot.org/c/coreboot/+/39847/13/src/soc/intel/tigerlake/me... File src/soc/intel/tigerlake/meminit_tgl.c:
https://review.coreboot.org/c/coreboot/+/39847/13/src/soc/intel/tigerlake/me... PS13, Line 306: if(channel == 0) { space required before the open parenthesis '('
https://review.coreboot.org/c/coreboot/+/39847/13/src/soc/intel/tigerlake/me... PS13, Line 307: if((info->topology == MEMORY_DOWN) || (info->topology == MIXED)) { space required before the open parenthesis '('
https://review.coreboot.org/c/coreboot/+/39847/13/src/soc/intel/tigerlake/me... PS13, Line 312: if((info->topology == SODIMM)) { Unnecessary parentheses - maybe == should be = ?
https://review.coreboot.org/c/coreboot/+/39847/13/src/soc/intel/tigerlake/me... PS13, Line 312: if((info->topology == SODIMM)) { space required before the open parenthesis '('
https://review.coreboot.org/c/coreboot/+/39847/13/src/soc/intel/tigerlake/me... PS13, Line 318: if(channel == 1) { space required before the open parenthesis '('
https://review.coreboot.org/c/coreboot/+/39847/13/src/soc/intel/tigerlake/me... PS13, Line 319: if(half_populated) { space required before the open parenthesis '('
https://review.coreboot.org/c/coreboot/+/39847/13/src/soc/intel/tigerlake/me... PS13, Line 324: if((info->topology == MEMORY_DOWN) || (info->topology == MIXED)) { space required before the open parenthesis '('
https://review.coreboot.org/c/coreboot/+/39847/13/src/soc/intel/tigerlake/me... PS13, Line 328: if((info->topology == SODIMM)) { Unnecessary parentheses - maybe == should be = ?
https://review.coreboot.org/c/coreboot/+/39847/13/src/soc/intel/tigerlake/me... PS13, Line 328: if((info->topology == SODIMM)) { space required before the open parenthesis '('
https://review.coreboot.org/c/coreboot/+/39847/13/src/soc/intel/tigerlake/me... PS13, Line 366: for (unsigned int i=0; i<DDR4_CHANNELS; i++) { spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/39847/13/src/soc/intel/tigerlake/me... PS13, Line 366: for (unsigned int i=0; i<DDR4_CHANNELS; i++) { spaces required around that '<' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/39847/13/src/soc/intel/tigerlake/me... PS13, Line 389: * DDR4x memory interface has 8 DQS pairs per channel. FSP UPDs for DQS Map expect a code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39847/13/src/soc/intel/tigerlake/me... PS13, Line 390: * pair in each UPD. code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39847/13/src/soc/intel/tigerlake/me... PS13, Line 391: * code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39847/13/src/soc/intel/tigerlake/me... PS13, Line 392: * Thus, init_dqs_upds() needs to be called for dqs pair of each channel. code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39847/13/src/soc/intel/tigerlake/me... PS13, Line 393: * DqsMapCpu2DramCh0 --> dqs_map[CHAN=0][0-1] code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39847/13/src/soc/intel/tigerlake/me... PS13, Line 394: * DqsMapCpu2DramCh1 --> dqs_map[CHAN=0][2-3] code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39847/13/src/soc/intel/tigerlake/me... PS13, Line 395: * DqsMapCpu2DramCh2 --> dqs_map[CHAN=0][4-5] code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39847/13/src/soc/intel/tigerlake/me... PS13, Line 396: * DqsMapCpu2DramCh3 --> dqs_map[CHAN=0][6-7] code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39847/13/src/soc/intel/tigerlake/me... PS13, Line 397: * DqsMapCpu2DramCh4 --> dqs_map[CHAN=1][0-1] code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39847/13/src/soc/intel/tigerlake/me... PS13, Line 398: * DqsMapCpu2DramCh5 --> dqs_map[CHAN=1][2-3] code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39847/13/src/soc/intel/tigerlake/me... PS13, Line 399: * DqsMapCpu2DramCh6 --> dqs_map[CHAN=1][4-5] code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39847/13/src/soc/intel/tigerlake/me... PS13, Line 400: * DqsMapCpu2DramCh7 --> dqs_map[CHAN=1][6-7] code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39847/13/src/soc/intel/tigerlake/me... PS13, Line 401: */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/39847/13/src/soc/intel/tigerlake/me... PS13, Line 404: for (int b = 0; b < DDR4_BYTES_PER_CHANNEL; b+=2) { spaces required around that '+=' (ctx:VxV)