Attention is currently required from: Jason Nien, Isaac Lee, Martin Roth, Tim Van Patten, Eric Peers, Karthikeyan Ramasubramanian.
Hello Jason Nien, Isaac Lee, Martin Roth, Tim Van Patten, Eric Peers, Karthikeyan Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69830
to look at the new patch set (#2).
Change subject: mb/google/skyrim/var/winterhold: Update DPTC setting for SMT ......................................................................
mb/google/skyrim/var/winterhold: Update DPTC setting for SMT
All parameters of DPTC_INPUT() need to be configured on devicetree when SOC_AMD_COMMON_BLOCK_ACPI_DPTC is enable. The parameters without configurations on devicetree would be 0 when SOC_AMD_COMMON_BLOCK_ACPI_DPTC is enable. Follow AMD DevHub document #57316. Configure vrm_current_limit_mA, vrm_maximum_current_limit_mA and vrm_soc_current_limit_mA on devicetree with thermal table config E as default table for SMT. Since the dynamic thermal table switching mechanism is still under cooking, after discussing with thermal team, suggest adopting config E(limit Soc not reach to max power) as default thermal config to avoid any thermal-related issue during phase build. Once the dynamic thermal table switching mechanism is finished, will change the default value to config A.
BUG=b:232946420, b:258572474 TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng ericky_cheng@compal.corp-partner.google.com Change-Id: Ic1e7a46cac4119c7237d96a7bd0d23c8db028680 --- M src/mainboard/google/skyrim/variants/winterhold/overridetree.cb 1 file changed, 26 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/69830/2