Felix Held has uploaded this change for review. ( https://review.coreboot.org/27706
Change subject: nehalem/raminit: remove REAL define and most dead code ......................................................................
nehalem/raminit: remove REAL define and most dead code
The code only compiled when REAL was set to 1; the other case included an unpublished include.
Change-Id: I7f31e9cd02f45492d6c9e88ec6164a537ca5e3c2 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/northbridge/intel/nehalem/raminit.c 1 file changed, 7 insertions(+), 79 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/27706/1
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index dcf9b7b..8c4d50e 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -14,13 +14,6 @@ * GNU General Public License for more details. */
-/* Please don't remove this. It's needed for debugging and reverse - * engineering more nehalem variants in the future. */ -#ifndef REAL -#define REAL 1 -#endif - -#if REAL #include <stdlib.h> #include <compiler.h> #include <console/console.h> @@ -45,22 +38,11 @@ #include <cpu/intel/turbo.h> #include <mrc_cache.h> #include <arch/early_variables.h> -#endif - -#if !REAL -typedef unsigned char u8; -typedef unsigned short u16; -typedef unsigned int u32; -typedef u32 device_t; -#endif
#include "nehalem.h"
#include <southbridge/intel/ibexpeak/me.h> - -#if REAL #include <delay.h> -#endif
#define NORTHBRIDGE PCI_DEV(0, 0, 0) #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) @@ -112,10 +94,6 @@ u32 reg_6e8; };
-#if !REAL -#include "raminit_fake.c" -#else - #include <lib.h> /* Prototypes */
static inline void write_mchbar32(u32 addr, u32 val) @@ -171,8 +149,6 @@ out[1] = ret.hi; }
-#endif - /* OK */ static void write_1d0(u32 val, u16 addr, int bits, int flag) { @@ -215,9 +191,7 @@
static void sfence(void) { -#if REAL asm volatile ("sfence"); -#endif }
static inline u16 get_lane_offset(int slot, int rank, int lane) @@ -232,7 +206,6 @@ return get_lane_offset(slot, rank, lane) + offs[(tm + 3) % 4]; }
-#if REAL static u32 gav_real(int line, u32 in) { // printk (BIOS_DEBUG, "%d: GAV: %x\n", line, in); @@ -240,7 +213,7 @@ }
#define gav(x) gav_real (__LINE__, (x)) -#endif + struct raminfo { u16 clock_speed_index; /* clock_speed (REAL, not DDR) / 133.(3) - 3 */ u16 fsb_frequency; /* in 1.(1)/2 MHz. */ @@ -1497,7 +1470,6 @@
memset(memory_map, 0, sizeof(memory_map));
-#if REAL if (info->uma_enabled) { u16 t = pci_read_config16(NORTHBRIDGE, D0F0_GGC); gav(t); @@ -1512,7 +1484,6 @@ uma_size_igd = uma_sizes_igd[(t >> 4) & 0xF]; uma_size_gtt = uma_sizes_gtt[(t >> 8) & 0xF]; } -#endif
mmio_size = get_mmio_size();
@@ -1543,7 +1514,7 @@ if (memory_remap) TOUUD -= quickpath_reserved;
-#if !REAL +#if 0 if (info->uma_enabled) { u16 t = pci_read_config16(NORTHBRIDGE, D0F0_GGC); gav(t); @@ -1685,7 +1656,6 @@
static void dump_timings(struct raminfo *info) { -#if REAL int channel, slot, rank, lane, i; printk(BIOS_DEBUG, "Timings:\n"); FOR_POPULATED_RANKS { @@ -1710,7 +1680,6 @@ info->training.reg_178); printk(BIOS_DEBUG, "[10b] = %x (%x)\n", read_1d0(0x10b, 6), info->training.reg_10b); -#endif }
/* Read timings and other registers that need to be restored verbatim and @@ -1750,7 +1719,6 @@ &train, sizeof(train)); }
-#if REAL static const struct ram_training *get_cached_training(void) { struct region_device rdev; @@ -1759,7 +1727,6 @@ return 0; return (void *)rdev_mmap_full(&rdev); } -#endif
/* FIXME: add timeout. */ static void wait_heci_ready(void) @@ -1842,10 +1809,6 @@ write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 2); do { csr.raw = read32(DEFAULT_HECIBAR + 0xc); -#if !REAL - if (i++ > 346) - return -1; -#endif } while (csr.csr.buffer_write_ptr == csr.csr.buffer_read_ptr); *(u32 *) head = read32(DEFAULT_HECIBAR + 0x8); @@ -3789,7 +3752,6 @@ write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) & ~1); }
-#if REAL static void dmi_setup(void) { gav(read8(DEFAULT_DMIBAR + 0x254)); @@ -3804,7 +3766,6 @@ DEFAULT_GPIOBASE | 0x38); gav(inb(DEFAULT_GPIOBASE | 0xe)); // = 0xfdcaff6e } -#endif
void chipset_init(const int s3resume) { @@ -3817,14 +3778,9 @@ printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); write_mchbar8(0x2ca8, 0); outb(0x6, 0xcf9); -#if REAL halt(); -#else - printf("CP5\n"); - exit(0); -#endif } -#if !REAL +#if 0 if (!s3resume) { pre_raminit_3(x2ca8); } @@ -3911,15 +3867,13 @@ /* before SPD */ timestamp_add_now(101);
- if (!s3resume || REAL) { + if (!s3resume || 1) { // possible error pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2); // = 0x80
collect_system_info(&info);
-#if REAL /* Enable SMBUS. */ enable_smbus(); -#endif
memset(&info.populated_ranks, 0, sizeof(info.populated_ranks));
@@ -4024,14 +3978,11 @@ timestamp_add_now(102);
write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) & 0xfc); -#if !REAL - rdmsr (MTRR_PHYS_MASK (3)); -#endif
collect_system_info(&info); calculate_timings(&info);
-#if !REAL +#if 0 pci_write_config8(NORTHBRIDGE, 0xdf, 0x82); #endif
@@ -4051,14 +4002,9 @@ printk(BIOS_INFO, "Interrupted RAM init, reset required.\n"); outb(0x6, 0xcf9); -#if REAL halt(); -#endif } } -#if !REAL - gav(read_mchbar8(0x2ca8)); ///!!!! -#endif
if (!s3resume && x2ca8 == 0) pci_write_config8(SOUTHBRIDGE, GEN_PMCON_2, @@ -4415,12 +4361,7 @@ write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) & ~3); write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) + 4); write_mchbar32(0x1af0, read_mchbar32(0x1af0) | 0x10); -#if REAL halt(); -#else - printf("CP5\n"); - exit(0); -#endif }
write_mchbar8(0x2ca8, read_mchbar8(0x2ca8)); @@ -4515,13 +4456,7 @@ reg32 = inl(DEFAULT_PMBASE + 0x04); outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); outb(0xe, 0xcf9); - -#if REAL halt(); -#else - printf("CP5\n"); - exit(0); -#endif } int tm; info.training = *info.cached_training; @@ -4781,10 +4716,6 @@ write_mchbar32(0xfa4, read_mchbar32(0xfa4) & ~0x01000002); write_mchbar32(0xfb0, 0x2000e019);
-#if !REAL - printf("CP16\n"); -#endif - /* Before training. */ timestamp_add_now(103);
@@ -4823,10 +4754,10 @@ write_mchbar8(0xff4, read_mchbar8(0xff4) | 0x2); // OK write_mchbar32(0xff8, (read_mchbar32(0xff8) & ~0xe008) | 0x1020); // OK
-#if REAL write_mchbar32(0xd00, IOMMU_BASE2 | 1); write_mchbar32(0xd40, IOMMU_BASE1 | 1); write_mchbar32(0xdc0, IOMMU_BASE4 | 1); +#if 1
write32p(IOMMU_BASE1 | 0xffc, 0x80000000); write32p(IOMMU_BASE2 | 0xffc, 0xc0000000); @@ -4963,9 +4894,8 @@ ax = read_mchbar16(0x1190) & 0xf00; // = 0x480a // OK write_mchbar16(0x1170, ax | (read_mchbar16(0x1170) & 0x107f) | 0x4080); // OK write_mchbar16(0x1170, read_mchbar16(0x1170) | 0x1000); // OK -#if REAL udelay(1000); -#endif + u16 ecx; for (ecx = 0xffff; ecx && (read_mchbar16(0x1170) & 0x1000); ecx--); // OK write_mchbar16(0x1190, read_mchbar16(0x1190) & ~0x4000); // OK @@ -4976,7 +4906,6 @@ udelay(10000); write_mchbar16(0x2ca8, 0x8);
-#if REAL udelay(1000); dump_timings(&info); cbmem_wasnot_inited = cbmem_recovery(s3resume); @@ -4996,5 +4925,4 @@ outb(0xe, 0xcf9); halt(); } -#endif }