[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add chip config for SATA strength

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38432 )

Change subject: soc/intel/cannonlake: Add chip config for SATA strength
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Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38432/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/38432/1//COMMIT_MSG@9 
PS1, Line 9: Add config to chip.h for tuning SATA gen3 strength.
Is there a bug for this so when it winds up in our tree it is visible to us?