Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51829 )
Change subject: mb/google/brya: change reset signal for GPP_F17 from PLTRST to DEEP ......................................................................
mb/google/brya: change reset signal for GPP_F17 from PLTRST to DEEP
PCH_INT_ODL (GPP_F17) is used to wake AP from S3, however it was configured to reset state on PLT reset assertion. This change reconfigures the pad using DEEP instead of PLTRST to retain pad configuration across S3.
BUG=b:178545523 TEST=manual: verified that asserting PCH_INT_ODL wakes system and the wake source is GPP_F17
Signed-off-by: Boris Mittelberg bmbm@google.com Change-Id: I8df5dafedabc7b6af74c39621f0e1eb7019a9a17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51829 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/brya/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/baseboard/gpio.c b/src/mainboard/google/brya/variants/baseboard/gpio.c index a777f79..9ff7720 100644 --- a/src/mainboard/google/brya/variants/baseboard/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/gpio.c @@ -242,7 +242,7 @@ /* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4), /* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, DEEP, LEVEL, INVERT), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ PAD_CFG_GPI(GPP_F18, NONE, DEEP), /* F19 : SRCCLKREQ6# ==> WWAN_SIM1_DET_OD */