[coreboot-gerrit] [M] Change in coreboot[main]: mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING

[Gareth Yu (Code Review)]

Attention is currently required from: Dinesh Gehlot, Eric Lai, Gareth Yu, Jayvik Desai, Kapil Porwal, Lawrence Chang, Nick Vaccaro, Paul Menzel, SH Kim, Simon Yang, Subrata Banik.

Gareth Yu has posted comments on this change by Lawrence Chang. ( https://review.coreboot.org/c/coreboot/+/86838?usp=email )

Change subject: mb/google/brya/var/meliks: reset DPHY_CLOCK_LANE_TIMING
......................................................................

Patch Set 28:

(7 comments)

File src/mainboard/google/brya/variants/meliks/ramstage.c:

https://review.coreboot.org/c/coreboot/+/86838/comment/3a1b263e_2e37545f?usp... :
PS17, Line 20: 0xf
> Will do.

Done

File src/mainboard/google/brya/variants/meliks/ramstage.c:

https://review.coreboot.org/c/coreboot/+/86838/comment/998418cc_81355629?usp... :
PS25, Line 10: REG_COMMAND						0x04
> Will do it.

Done

https://review.coreboot.org/c/coreboot/+/86838/comment/dd4ed661_744b1796?usp... :
PS25, Line 12: 
             : #define REG_COMMAND_BM					(1 << 2)
             :
> Will do it.

Done

https://review.coreboot.org/c/coreboot/+/86838/comment/325bb278_842dff1a?usp... :
PS25, Line 38: TEMP_IGD_ADDRESS
> Will do it.

Done

File src/mainboard/google/brya/variants/meliks/ramstage.c:

https://review.coreboot.org/c/coreboot/+/86838/comment/973c04b0_fdd767c4?usp... :
PS26, Line 24:
>

Done

https://review.coreboot.org/c/coreboot/+/86838/comment/09f91eb0_dd2a0758?usp... :
PS26, Line 31: if (!igd_base) {
             : 		need_temp_bar = true;
             : 		igd_base = CONFIG_GFX_GMA_DEFAULT_MMIO;
             : 		pci_write_config32(SA_DEVFN_IGD, PCI_BASE_ADDRESS_0, igd_base);
             : 		igd_cmd = pci_read_config16(SA_DEVFN_IGD, PCI_COMMAND);
             : 		pci_write_config16(SA_DEVFN_IGD, PCI_BASE_ADDRESS_0, igd_cmd | PCI_COMMAND_MEMORY);
             : 	}
>

Done

https://review.coreboot.org/c/coreboot/+/86838/comment/cce90810_162fd822?usp... :
PS26, Line 41: 	if (need_temp_bar) {
             : 		pci_write_config16(SA_DEVFN_IGD, PCI_COMMAND, igd_cmd & ~PCI_COMMAND_MEMORY);
             : 		pci_write_config32(SA_DEVFN_IGD, PCI_BASE_ADDRESS_0, 0);
             : 	}
>

Done