[coreboot-gerrit] [S] Change in coreboot[main]: soc/amd/common/block: Cache ROM3

[Patrick Rudolph (Code Review)]

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier.

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86620?usp=email )

Change subject: soc/amd/common/block: Cache ROM3
......................................................................

soc/amd/common/block: Cache ROM3

Mark ROM3 as cached in bootblock entry as done for ROM2.
Mark ROM3 as cached after MP-init as done for ROM2.

Change-Id: I2df51ee3f492e5a80f5ee2676196830045dcdeb3
Signed-off-by: Patrick Rudolph 
---
M src/soc/amd/common/block/cpu/noncar/early_cache.c
M src/soc/amd/common/block/cpu/noncar/mpinit.c
2 files changed, 25 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/86620/1

diff --git a/src/soc/amd/common/block/cpu/noncar/early_cache.c b/src/soc/amd/common/block/cpu/noncar/early_cache.c
index 8c5fbc3..887ea68 100644
--- a/src/soc/amd/common/block/cpu/noncar/early_cache.c
+++ b/src/soc/amd/common/block/cpu/noncar/early_cache.c
@@ -2,6 +2,7 @@

#include <amdblocks/cpu.h>
 #include <amdblocks/iomap.h>
+#include <amdblocks/lpc.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/msr.h>
@@ -64,6 +65,18 @@
    var_mtrr_set(&mtrr_ctx.ctx, FLASH_BELOW_4GB_MAPPING_REGION_BASE,
    	     FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT);

+	/* ROM3 is only accessible in x86_64. Only required when ROM2 doesn't cover whole flash. */
+	if (CONFIG(SOC_AMD_COMMON_BLOCK_SPI_MMAP_USE_ROM3)) {
+		size_t rom3_size = 0;
+		uint64_t rom3_start = lpc_get_rom3_region(&rom3_size);
+
+		if (rom3_start && rom3_size) {
+			/* The flash is now no longer cacheable. Reset to WP for performance. */
+			rom3_size = 1 << log2_ceil(rom3_size);
+			var_mtrr_set(&mtrr_ctx.ctx, rom3_start, rom3_size, MTRR_TYPE_WRPROT);
+		}
+	}
+
    commit_mtrr_setup(&mtrr_ctx.ctx);

/* Set up RAM caching for everything below 1MiB except for 0xa0000-0xc0000 . */
diff --git a/src/soc/amd/common/block/cpu/noncar/mpinit.c b/src/soc/amd/common/block/cpu/noncar/mpinit.c
index 002c505..00b8a207 100644
--- a/src/soc/amd/common/block/cpu/noncar/mpinit.c
+++ b/src/soc/amd/common/block/cpu/noncar/mpinit.c
@@ -2,6 +2,7 @@

#include <acpi/acpi.h>
 #include <amdblocks/iomap.h>
+#include <amdblocks/lpc.h>
 #include <console/console.h>
 #include <cpu/x86/mp.h>
 #include <cpu/x86/mtrr.h>
@@ -20,6 +21,17 @@
    mtrr_use_temp_range(FLASH_BELOW_4GB_MAPPING_REGION_BASE,
    		    FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT);

+	if (CONFIG(SOC_AMD_COMMON_BLOCK_SPI_MMAP_USE_ROM3)) {
+		size_t rom3_size = 0;
+		uint64_t rom3_start = lpc_get_rom3_region(&rom3_size);
+
+		if (rom3_start && rom3_size) {
+			/* The flash is now no longer cacheable. Reset to WP for performance. */
+			rom3_size = 1 << log2_ceil(rom3_size);
+			mtrr_use_temp_range(rom3_start, rom3_size, MTRR_TYPE_WRPROT);
+		}
+	}
+
    /* SMMINFO only needs to be set up when booting from S5 */
    if (!acpi_is_wakeup_s3())
    	apm_control(APM_CNT_SMMINFO);