[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso: Add FSP support for including AGESA

[Marshall Dawson (Code Review)]

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34423 )

Change subject: soc/amd/picasso: Add FSP support for including AGESA
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Patch Set 27:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34423/27/src/soc/amd/picasso/romsta... 
File src/soc/amd/picasso/romstage.c:

https://review.coreboot.org/c/coreboot/+/34423/27/src/soc/amd/picasso/romsta... 
PS27, Line 34: 	/* Disable WB from to region 4GB - TOM2 */
> I'm curious why we are doing this from a policy standpoint.

AGESA has always set MTRRs and the default caching.  We went through this with Stoney Ridge as well until it was removed from that version of AGESA.  So the intent was to restore settings to a pre-AGESA state.

Maybe this could be in CB:40922 too.  And rather than jamming it to the default setting, rewrite SYS_CFG if it was modified by AGESA (possibly certain bits).