Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46471 )
Change subject: soc/intel/common/acpi,mb/*: replace the two obsolete LPID with PEPD ......................................................................
soc/intel/common/acpi,mb/*: replace the two obsolete LPID with PEPD
Replace the two obsolete LPID implementations with the new PEPD device.
The PEPD device gets included in the plaforms' `southbridge.asl`, since it is required to load the `intel_pmc_core` module in Linux, which checks for the _HID. (See CB:46469 for more info on that.)
There is no harm for mainboards not supporting S0ix, because the _DSM function won't be called with the LPS0 UUID on such boards. Such boards can use the debugging functionality of `intel_pmc_core`, too.
Change-Id: Ic8427db33286451618b50ca429d41b604dbb08a5 Signed-off-by: Michael Niewöhner foss@mniewoehner.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/46471 Reviewed-by: Furquan Shaikh furquan@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/deltaur/dsdt.asl M src/mainboard/google/drallion/dsdt.asl M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/sarien/dsdt.asl M src/mainboard/google/volteer/dsdt.asl M src/soc/intel/alderlake/acpi/southbridge.asl M src/soc/intel/cannonlake/acpi/southbridge.asl D src/soc/intel/common/acpi/lpit.asl D src/soc/intel/common/block/acpi/acpi/pmc.asl M src/soc/intel/elkhartlake/acpi/southbridge.asl M src/soc/intel/jasperlake/acpi/southbridge.asl M src/soc/intel/tigerlake/acpi/southbridge.asl 12 files changed, 10 insertions(+), 137 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/deltaur/dsdt.asl b/src/mainboard/google/deltaur/dsdt.asl index 206119f..1bca44f 100644 --- a/src/mainboard/google/deltaur/dsdt.asl +++ b/src/mainboard/google/deltaur/dsdt.asl @@ -35,9 +35,6 @@ /* VPD support */ #include <vendorcode/google/chromeos/acpi/vpd.asl>
- /* Low power idle table */ - #include <soc/intel/common/acpi/lpit.asl> - /* Chrome OS Embedded Controller */ Scope (_SB.PCI0.LPCB) { diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index a6abdb8..92fa2b8 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -39,9 +39,6 @@
#include <southbridge/intel/common/acpi/sleepstates.asl>
- /* Low power idle table */ - #include <soc/intel/common/acpi/lpit.asl> - /* Chrome OS Embedded Controller */ Scope (_SB.PCI0.LPCB) { diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index d2170d0..1395c8f 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -36,9 +36,6 @@
#include <southbridge/intel/common/acpi/sleepstates.asl>
- /* Low power idle table */ - #include <soc/intel/common/acpi/lpit.asl> - /* Chrome OS Embedded Controller */ Scope (_SB.PCI0.LPCB) { diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index 98aa54a..664305e 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -39,9 +39,6 @@
#include <southbridge/intel/common/acpi/sleepstates.asl>
- /* Low power idle table */ - #include <soc/intel/common/acpi/lpit.asl> - #if CONFIG(EC_GOOGLE_WILCO) /* Chrome OS Embedded Controller */ Scope (_SB.PCI0.LPCB) diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index cf73367..ba9541e 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -38,10 +38,6 @@ // Chrome OS specific #include <vendorcode/google/chromeos/acpi/chromeos.asl>
- /* Include Low power idle table for a short term workaround to enable - S0ix. Once cr50 pulse width is fixed, this can be removed. */ - #include <soc/intel/common/acpi/lpit.asl> - // Chrome OS Embedded Controller Scope (_SB.PCI0.LPCB) { diff --git a/src/soc/intel/alderlake/acpi/southbridge.asl b/src/soc/intel/alderlake/acpi/southbridge.asl index 42f3b12..3d8e554 100644 --- a/src/soc/intel/alderlake/acpi/southbridge.asl +++ b/src/soc/intel/alderlake/acpi/southbridge.asl @@ -44,8 +44,8 @@ /* PCI _OSC */ #include <soc/intel/common/acpi/pci_osc.asl>
-/* PMC Core*/ -#include <soc/intel/common/block/acpi/acpi/pmc.asl> +/* Intel Power Engine Plug-in */ +#include <soc/intel/common/block/acpi/acpi/pep.asl>
/* GbE 0:1f.6 */ #include <soc/intel/common/block/acpi/acpi/pch_glan.asl> diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 35dc196..fafbbfd 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -46,5 +46,5 @@ /* GbE 0:1f.6 */ #include <soc/intel/common/block/acpi/acpi/pch_glan.asl>
-/* PMC Core */ -#include <soc/intel/common/block/acpi/acpi/pmc.asl> +/* Intel Power Engine Plug-in */ +#include <soc/intel/common/block/acpi/acpi/pep.asl> diff --git a/src/soc/intel/common/acpi/lpit.asl b/src/soc/intel/common/acpi/lpit.asl deleted file mode 100644 index 6159685..0000000 --- a/src/soc/intel/common/acpi/lpit.asl +++ /dev/null @@ -1,103 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#define LPID_DSM_ARG2_ENUM_FUNCTIONS 0 -#define LPID_DSM_ARG2_GET_DEVICE_CONSTRAINTS 1 - -#define LPID_DSM_ARG2_GET_CRASH_DUMP_DEV 2 -#define LPID_DSM_ARG2_DISPLAY_OFF_NOTIFY 3 -#define LPID_DSM_ARG2_DISPLAY_ON_NOTIFY 4 -#define LPID_DSM_ARG2_S0IX_ENTRY 5 -#define LPID_DSM_ARG2_S0IX_EXIT 6 - -External(_SB.MS0X, MethodObj) -External(_SB.PCI0.LPCB.EC0.S0IX, MethodObj) -External(_SB.PCI0.EGPM, MethodObj) -External(_SB.PCI0.RGPM, MethodObj) - -Scope(_SB) -{ - Device(LPID) - { - Name(_ADR, 0x00000000) - Name(_CID, EISAID("PNP0D80")) - Name(UUID, ToUUID("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66")) - Method(_DSM, 4) - { - If(Arg0 == ^UUID) { - /* - * Enum functions - */ - If(Arg2 == LPID_DSM_ARG2_ENUM_FUNCTIONS) { - Return(Buffer(One) {0x60}) - } - /* - * Function 1 - Get Device Constraints - */ - If(Arg2 == LPID_DSM_ARG2_GET_DEVICE_CONSTRAINTS) { - Return(Package(5) {0, Ones, Ones, Ones, Ones}) - } - /* - * Function 2 - Get Crash Dump Device - */ - If(Arg2 == LPID_DSM_ARG2_GET_CRASH_DUMP_DEV) { - Return(Buffer(One) {0x0}) - } - /* - * Function 3 - Display Off Notification - */ - If(Arg2 == LPID_DSM_ARG2_DISPLAY_OFF_NOTIFY) { - } - /* - * Function 4 - Display On Notification - */ - If(Arg2 == LPID_DSM_ARG2_DISPLAY_ON_NOTIFY) { - } - /* - * Function 5 - Low Power S0 Entry Notification - */ - If(Arg2 == LPID_DSM_ARG2_S0IX_ENTRY) { - /* Inform the EC */ - If (CondRefOf (_SB.PCI0.LPCB.EC0.S0IX)) { - _SB.PCI0.LPCB.EC0.S0IX(1) - } - - /* provide board level S0ix hook */ - If (CondRefOf (_SB.MS0X)) { - _SB.MS0X(1) - } - - /* - * Save the current PM bits then - * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG - */ - If (CondRefOf (_SB.PCI0.EGPM)) - { - _SB.PCI0.EGPM () - } - } - /* - * Function 6 - Low Power S0 Exit Notification - */ - If(Arg2 == LPID_DSM_ARG2_S0IX_EXIT) { - /* Inform the EC */ - If (CondRefOf (_SB.PCI0.LPCB.EC0.S0IX)) { - _SB.PCI0.LPCB.EC0.S0IX(0) - } - - /* provide board level S0ix hook */ - If (CondRefOf (_SB.MS0X)) { - _SB.MS0X(0) - } - - /* Restore GPIO all Community PM */ - If (CondRefOf (_SB.PCI0.RGPM)) - { - _SB.PCI0.RGPM () - } - } - } - - Return(Buffer(One) {0x00}) - } // Method(_DSM) - } // Device (LPID) -} // End Scope(_SB) diff --git a/src/soc/intel/common/block/acpi/acpi/pmc.asl b/src/soc/intel/common/block/acpi/acpi/pmc.asl deleted file mode 100644 index ddf6470..0000000 --- a/src/soc/intel/common/block/acpi/acpi/pmc.asl +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Device (PEPD) -{ - Name (_HID, "INT33A1" /* Intel Power Engine */) - Name (_CID, EisaId ("PNP0D80") /* System Power Management Controller */) - Name (_UID, One) -} diff --git a/src/soc/intel/elkhartlake/acpi/southbridge.asl b/src/soc/intel/elkhartlake/acpi/southbridge.asl index 28705b1..17d1913 100644 --- a/src/soc/intel/elkhartlake/acpi/southbridge.asl +++ b/src/soc/intel/elkhartlake/acpi/southbridge.asl @@ -41,8 +41,8 @@ /* PCI _OSC */ #include <soc/intel/common/acpi/pci_osc.asl>
-/* PMC Core*/ -#include <soc/intel/common/block/acpi/acpi/pmc.asl> +/* Intel Power Engine Plug-in */ +#include <soc/intel/common/block/acpi/acpi/pep.asl>
/* EMMC/SD card */ #include "scs.asl" diff --git a/src/soc/intel/jasperlake/acpi/southbridge.asl b/src/soc/intel/jasperlake/acpi/southbridge.asl index b82cce5..ebc6fd8 100644 --- a/src/soc/intel/jasperlake/acpi/southbridge.asl +++ b/src/soc/intel/jasperlake/acpi/southbridge.asl @@ -47,8 +47,8 @@ /* PCI _OSC */ #include <soc/intel/common/acpi/pci_osc.asl>
-/* PMC Core*/ -#include <soc/intel/common/block/acpi/acpi/pmc.asl> +/* Intel Power Engine Plug-in */ +#include <soc/intel/common/block/acpi/acpi/pep.asl>
/* EMMC/SD card */ #include "scs.asl" diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl index 42f3b12..3d8e554 100644 --- a/src/soc/intel/tigerlake/acpi/southbridge.asl +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -44,8 +44,8 @@ /* PCI _OSC */ #include <soc/intel/common/acpi/pci_osc.asl>
-/* PMC Core*/ -#include <soc/intel/common/block/acpi/acpi/pmc.asl> +/* Intel Power Engine Plug-in */ +#include <soc/intel/common/block/acpi/acpi/pep.asl>
/* GbE 0:1f.6 */ #include <soc/intel/common/block/acpi/acpi/pch_glan.asl>